Placements checks

• Congestion
• If the congestion is there in your design first check in which region you got the congestion hotspot
• If it is with cell density use partial blockage , how much percentage you gave to clear the congestion hotspot 
• If it is due to pin density , Use cell padding /keep_out_margin ,how much padding number you gave and for which cell/instance/module
• If congestion is there at Macro pins , think about how to resolve the issue 
• First check is there any sufficient Blockage or not if it is not there give proper blockage
• keep out margin will also helps 
• You may see the shorts on macro pins with routing blockage on it ,so you should reduce the route blockage area on macro 
• Check the channel spacing is there or not otherwise you may see the congestion
• Remember in which metal layer, you got the congestion 
• Timing
• You should take care about the setup time violations not for Hold time violations but it should be under control
• why we did not check the hold time violations at this stage means clock is not yet build, the delay or not real these delays are estimated delays
• If you get the setup time violations check about the flop location, if it is too far use bounds
• Even though setup time is not fixed ,Get the all nets which are there in that path and  you can route it in top metal layer by using specify_net_weight
• Use net guides also you fix the setup time violations set_net_priority which metal layers are used to route first
• If the combinational delay  is more than the clock period you should inform to RTL Team, based on there guidelines use multi_cycle paths
• what is the uncertainty, how much value is there for setup and hold uncertainty 
• What is latency,how much value you gave for both source and network latency
• If data to data to data check is required for a particular module or module ports 
• Density
• check Placement Density
• If the pin density is more ,you have to check the don't touch or don't use attribute on the cells ,If these attributes are not specified tool may use those cells 

PowerPlan checks

• Power nets  opens
• Power nets shorts
• No of stripes
• Set to set distance
• Ring width
• Which metal layers are used for power route (For ring and stripes)
• Power hook up was done are not 
• Early rail analysis
• Electro migration and IR drop analysis only for power nets 

Floor plan cheeks

Sanity checks were done after that

• Utilization
• Aspect ratio
• IO clearance
• block size
• Area
• pin/port placement
• Macro placement
• offset value
• Macro orientation
• channel spacing between macros
• Placement blockages
• keep_out margin for macros

ICC commands frequently used at CTS stage

• get_clocks
• get_property [get_clocks clock_name] period
• get_property [get_clocks clock_name] uncertainty
• get_property [get_clocks clock_name] latency
• sizeof_collections [get_clocks]
• report_clock_tree
• report_clock_tree -exceptions
• report_clock_tree -level_info
• report_clock_tree -summary
• report_clock_tree -type latency
• report_clock_tree -local_skew
• get_utilization
• get_buffers  *CLK* 
• set_dont_touch [get_lib_cells */*DLY*] false
• set_dont_touch [get_lib_cells */*CLKBUF*] false
• set_dont_touch [get_lib_cells */*CLKINV*] false
• report_clock_tree_power
• report_clock_tree -interclock_timing
• report_clock_timing -type latency

Report_timing

 Report_timing Switches

• report_timing -late
• report_timing -early
• report_timing -from u123/y -to u124/b
• report_timing -from u123/y -through u124/b -to reg/D
• report_timing -path_type max -path_group r2r 
• report_timing -max_paths 50 -nworst 500
• report_timing -slack_lessor_than 0 -delay_type max
• report_timing -slack_greater_than 0 -delay_type min
• report_timing -format {cell arc instance slack startPoint endPoint}
• report_timing -collection [get_clocks clock_name]

Virtual clock

 Virtual clock 

• Virtual clock is a clock it is doesn't associated with any clock pin or Port of the design
• it will be used to validate the input to output timing paths
• It is reference to static timing analysis to validate the reg2out ,in2out paths or in2reg paths

Data Arrival time and Data required time

 Data Arrival Time:

• Time taken by the signal to propagate from clock definition point  to the D pin of the capturing flop is called as data arrival time
• DAT = Tlaunch + Tcq+Tcombo+net delays

Data required time:

• Data required time is the time taken by the signal from clock definition point to the clock pin of the capturing flop is called as the data required time
• DRT = Tclk +Tcapture +clock logic Delay -Tsetup -Tuncrtainty+clock net delay for setup time analysis

Transition, Slew, skew and cell Delay

 Transition:

• Time taken by the signal can change their state from 0 to 1 or 1 to 0 is called as the Transition

Slew:

• The rate of change of transition is called as Slew 

Skew:

• The clock path arrival difference between the two successive clocks is called as Skew

Cell Delay:

• Cell delay is based on input transition and output load is called as cell delay 
• This delay is based on cell rise and cell fall delay

Floor plan commands in innovus

 Floor plan Reports

1. checkFPlan -reportUtil
2. checkPlace
3. Check_timing -verbose
4. CheckNetlist
5. CheckUnique
6. Report_qor
7. Report_timing
8. checkPinAssignment
9. checkDesign -all
10. report_constraints
11. all_analysis_views
12. report_analysis_summary

Latency

Clock Latency

•  Latency is the combination of both source latency and network latency 
• Clock Latency = source latency + Network latency

source latency:

Time taken by the signal to propagate from the clock source to clock definition point

Network latency: 

Time is taken by the signal to propagate from clock definition point to register clock pin

How to give the latency target by command 

• set_clock_latency 0.2 -rise [get_clocks clock] 
• set_clock_latency 0.1 -fall [get_clocks clock]

If we don't specify the  -source switch tool automatically it consider as a network latency

• set_clock_latency  -source 0.300 -early [get_clocks clock]
• set_clock_latency  -source 0.400 -late [get_clocks clock] 

How to reduce the cross talk

 Cross talk reduction techniques:

• Use the shielding
• Apply NDR rules
• Double space will help you to reduce the cross talk
• down sizing the Aggressor net Driver cell
• Upsize the Victim net driver cell 

Blockages

Soft (Non buffer blockage)

• Only buffers can be placed and standard cells cannot be placed.

Hard (Std-cell blockage)

• Blocks all std-cells and buffers to be placed. 
• Std-cell blockages are mostly used to:
• Avoid routing congestion at macro corners
• Restrict std-cells to certain regions in the design
• Control power rails generation at macro cells

Partial blockages

• By default a placement blockage has a blockage factor of 100%. No cells can be placed in that area, but flexibility of blockages can be chosen by partial blockages.
• To reduce placement density without blocking 100% of the area, changing the blockage factor of an existing blockage to lower value will be a better option.

Benefits 

• Reduce the congestion by spreading the logic

Disadvantages

• It may leads to timing violations
• Hard blockages will west the core area

Commands to create the placement blockages

• create_placement_blockage -coordinates { {x1 y1} {x2 y2}} -type hard/Soft -name blockagename
• create_placement_blockage -coordinates { {x1 y1} {x2 y2}} -type partial -blocked_percentage x -name blockagename.

Cross talk

 Cross talk:

• Cross talk is nothing but ,switching in one net can interfere neighbouring net due to the cross coupling capacitance between that , this is called as cross talk
• switching signal is Aggressor
• Non switching signal is victim

 Effects of Cross talk

• Cross talk leads to timing violations
• Functional failure

How cross talk will impact on the timing

• case 1
• If the signal is switching in same direction , victim transition becomes fast resulting data to arrival early which leads to hold violations
• This scenario is good for setup and bad for hold
• case 2
• if the signal is switching in opposite directions , victims transition becomes slows down ,which  increasing the delay and leads to setup violation
• This scenario is good for hold and bad for setup
• case 3 
• If cross talk in clock path the above cases are opposite 

Note

Same Direction means 

• Aggressor and victim signal state are changing from 0 to 1

Opposite Directions means

• Aggressor is switching from 0 to 1 and victim is switching from 1 to 0

Conditions for above 3 cases are , when Switching window will match then only timing violations will come otherwise noise will come

Which is cell better buffer cell or Inverter cell Why ?

 Inverter is Better than the Buffer because 

• Better transition than buffer
• Size is less
• Less Dynamic power consumption 
• Reducing the duty cycle distortion

Technology File (.tf)

Technology File (.tf)

Fabrication Team will provide the Technology File
Technology file (.tf) in Synopsys Format

Tech_lef in Cadence Format

Technology file contains

• Units
• Max current density
• Metals 
• Layers
• Vias
• Min width
• Min space
• Pitch
• Lines
• Patterns
• Intensity
• Metal Density
• Antenna Rules
• Width 
• Height
• Blink
• Color names
• Mask Name

LEF (Library Exchange Format)

LEF (Library Exchange Format(.lef)):

Types of LEFS

• Std.cell LEF

• Macro LEF

• IO Lef

LEF Contains

• Cell
• Cell name
• Shape
• Pin Size
• Orientation
• Class
• Pin Name
• Pin layer name
• Port Name
• Layout Geometries
• Blockage
• Pin Depth
• Pin spacing
• Pin width
• Antenna Diff Area

LIB (Libraries (.Lib))

 Libraries (liberty file .libs) :

Vendor will provide the Libraries

Cell Delay = based on input transition and output load

• Units
• Library Setup time
• Library Hold time
• Removal time
• Recovery time
• Leakage Power
• Dynamic Power
• Delay
• PVT conditions
• Wire load models
• Std.lib
• Macro.lib
• IO lib
• Arcs
• Input transition
• Output load

Gate level Netlist (.V)

Gate level Netlist (.V)

Synthesis team will provide the Gate level Netlist (.V) file

It is the combination of the sequential and combinational cells and its connectivity

it contains 

• Module

• Module Information

• Cell & Instance name

• Drive strength

• Inputs

• Outputs

• Wire Information

• Hierarchy Information

• Sub-Module Names

Example :

Module andGate (a b c);

input a , b;

output c;

and2x1 g1 (c,a,b) ;

endmodule

Bottleneck Analysis

• If a single Cell is a part of multiple paths and is the root cause of violations in all those paths, then that Cell can be considered as a bottleneck in the design
• Bottleneck Analysis lists these types of cells causing timing violations on multiple paths
• By identifying and fixing the violation caused by a Bottleneck Cell improved timing can be achieved
  
  

• You fix many violations with one change 

Multi cycle paths

• Multi Cycle path is nothing but the data can take more than one clock cycle to capture the data is called as multi cycle path.
• Multi cycle path is a one of the timing Exception
• This timing exception is created between the inter clock domains  
• The domain relationship between the clocks used in multi cycle path

how to set the multi cycle path:

• case 1
• To set the multi cycle path between the flops
• set_multicycle_path -from flop1 -to flop2
• case 2
• Between the clock domains
• set_multicycle_path -from clock1 -to clock2
• case 3

• How to set the multi cycle path for setup and hold
• set_multicycle_path  5 -setup -from [get_clocks clock1] -to [get_clocks clock2]
• set_multicycle_path  4 -hold -from [get_clocks clock1] -to [get_clocks clock2]
• case 4 
• If clock 1 is faster than the clock2
• set_multicycle_path  5 -setup -from [get_clocks clock1] -to [get_clocks clock2] -start
• set_multicycle_path  4 -hold -from [get_clocks clock1] -to [get_clocks clock2] -start
• case 5
• if clock 1 is slower than the clock2
• set_multicycle_path  5 -setup -from [get_clocks clock1] -to [get_clocks clock2] -end
• set_multicycle_path  4 -hold -from [get_clocks clock1] -to [get_clocks clock2] -end

• Note:
• Multi cycle path number is based on the requirement
• if you do multi cycle for setup analysis Nth edge ,you have to do hold analysis at N-1 edge
• based on the fast clock we should put the start and end switch
• if the faster clock is at launching side you should keep start otherwise put end switch

• Benefits of the multi cycle path

• Multi cycle path will improve the timing

Scan DEF

SCAN DEF file contains

• Group of scan chains ,these are called as partitions
• Where we need to start the scan chain ,and where we need to end the scan chain flop info
• How many flops are there for each chain
• A partition can have only one operating condition and power domain

Scan chain Reordering

• The scan Flip flop placements may create lengthier routes if the consecutive flops in scan chain placement far due to a functional requirement
• In this case, the Place and Route tool can reconnect the scan chain to make routing easier
• The scan chain reordering is performed at Placement 
• scan chain can reduce the wire length and congestion
• scan chain will improve  the routability
• scan chain can performed based on their physical location of the flops

Benefits with the Scan chain reordering:

• Lesser the length will reduce the resistance and capacitance
• Lower values of  R and C will improve the timing
• It will reduce the congestion

Useful Skew

 Useful Skew

• By intentionally adding some delay to in the clock path at clock pin of capture path or launch path is called as Useful skew

Consider the above figure

• The above figure has two timing paths from F1 to F2 and From F2 to F3
• There is timing violation in first timing path , We have setup margin in F2 to F3
• By adding some delay to the clock pin of the Flop F2 , it will fix the setup time violation

• Example DRT is 500 ps ,DAT is 600 ps , setup is violated with 100 ps

• consider From Flop F1 to Flop F2, there is timing violation of -100 pico sec, setup slack = DRT-DAT, hold is 200ps
• From Flop F2 to Flop F3 ,there is a setup margin of 500ps and hold margin of 100ps

• Obsevartions

1. After adding the delay to the clock pin of the flop F2 , setup got fixed between the F1 and F2 but hold time may failure we should take care of that, based on the margin and hold slack we can add the delay 
2. Between the F2 and F3 setup may violate but hold may benefit,  if we add more delay to the clock pin of the F2

Care fully observe the below figure 

Filler cells

Fillers cells

• These cells are Physical only cells , there is no logical connection
• These cells are useful for Nwell continuity,Power continuity and Implantation layer in Design
• If N wells are Discontinuity DRC will Fill the Filler cells based on the gap 

What is the need of the Nwell continuity

• Nwells and implantation are continuous it is easier to foundry people to generate the mask 
• Mask is very costly

############### adding filler cells############################

• addFiller -cell {FILL1 FILL2 FILL4 FILL8 FILL16 FILL32} -prefix filler_cells

Manufacturing Grid, standard cell row and Unit tile

 Manufacturing Grid :

• The smallest geometry that semiconductor foundry can process or smallest resolution of your technology process (e.g. 0.005)
• All drawn geometries during Physical Design must snap to this grid
• While Masking fab. use this as reference line

Standard Cell Site/ Standard Cell Placement Tile/ Unit Tile

• The minimum Width and Height a Cell that can occupy in the design
• The Standard Cell Site will have the same height as Standard Cells, but the width will be as small as your smallest Filler Cell
• It’s one Vertical Routing Track and the Standard Cell Height
• All Standard Cells must be multiple of Unit Tile

Standard Cell Rows

• Rows are actually the Standard Cell Sites abut side by side and then Standard Cells are placed on these Rows
• Cells with the equal no. of Track definition will have same height

what is the Difference between PBA and GBA

Path based analysis Vs Graph based analysis 

• In GBA mode the tool consider both the worst slew and worst arrival in a path during the analysis
• In PBA mode the tool consider the path by  path 
• for setup analysis ,in GBA it will consider worst values among all the four values (observe the below picture), For PBA it will consider path by path and timing arc by  timing arc
• For hold analysis, in GBA it will consider best value (less value) among all the four values
• Conclusion is GBA is more pessimistic than PBA
• PBA with AOCV is the Best Timing 
• mindelay _GBa <= mindelay PBA
• max_delay GBA >= max_delay in PBA

How to fix the Transition Violations

Transition Fixing Techniques

• Up-sizing the Driver cell
• Adding the Buffer at beginning of the driver net
• Split the Load 

What are the reasons for metastability

 Reasons for Meta-stability

• Slow transition
• Less supply voltage
• High clock skew
• Excessive combo delay 

How electromigration will impact on the Timing

 Electromigration: 

• For fixes of the Electro migration violations ,will increase the width of the metal layers 
• If will increase the metal width of that net ,the net resistance capacitance will decrease it leads to fastened the data
• Due to that that, the delay of the metal layer will decrease 
• Due to lesser values of the R and C the transition of that metal layer may increase it leads to hold time violations
• This timing violations are based on the life time of the chip

Electro_migration and it's Fixing techniques

 Electro_migration:

• Electro migration is nothing but , the current in a metal wire is more than the current carrying capability of that metal wire is called Electro migration 
• Electro migration can lead to opens or shorts due to metal ion displacement caused by the flow of electrons
• Electro migration will come in both Power ans Signal nets
• Power Em is more crucial than signal em because the current direction in the power net is uni direction but in signal both the direction that's why less electromigration in  signal nets compared to power nets

Electro migration Fixing techniques

• Increasing the Metal width will to fix the electromigration ,which means if you increase the metal width the current carrying capability of that metal wire will increase , means the current density will reduce 
• current density = current / area
• Area =width x thickness
• sigma = current /W*T
• current density and width is inversely proportional 
• Metal jumping Top metal layers also a one of the technique because Top metal layer width is high compared to lower metal layers
• Non Default rules double width will help to fix the em violation

How IR Drop will impact on Timing

 IR Drop

• IR drop will occur due to the internal resistance, capacitance factors of the net . instance or cell may not get the sufficient voltage to drive the cell is called IR Drop
• Due to IR Drop cell may not work properly because the cell didn't get the sufficient supply voltage
• Due to this DROP the output of the cell may take lot of time to store the output of the that instance or cell it leads fail the timing

How It will impact on the timing:

• Due to that Ir drop , cell output may take lot of time it leads to setup time violation 

Reasons:

• Consider two flops are connected in cascade
• Assume 1st Flop is launching flop and second flop is Capturing Flop
• Due to the internal resistance and cap values the data can go slow in data path which means it may take time
• When data path is slower than the clock path it leads to Setup time violation
• IR drop will help to Hold time Violations
• If IR drop is more in the clock path it may get both setup and hold violation

What Does DEF file contains

• Contains Die/core area
• Placed Macro information
• Blockage information
• Placed I/O Pin/pad information
• std cell placement area

What are Physical DRC's

• Minimum width and spacing for metal
• Minimum width and spacing for via
• End of line spacing
• Via Enclose
• Parallel length spacing
• Minimum area
• Misaligned net Spacing
• Non sufficient Metal overlap
• Shorts violations
• Less than min edge Length
• Different net via cut spacing
• Special notch spacing

How to add Metal Fills

 ############## Adding Metal fills ##############################

• setMetalFill -maxDensity based_on_node -minDensity based_on_node -layer {Metal1 Metal2 Metal3 Metal4 Metal5 Metal6 Metal7 Metal 8 Metal9} 
• addMetalFill -layer {Metal1 Metal2 Matel3 Metal4 Metal5 Metal6 Metal7 Metal 8 Metal9 } -timingAware sta -net {VSS}

Note : Metal layers are Based On the Design

Adding Filler cells

 ############### adding filler cells############################

• addFiller -cell {FILL1 FILL2 FILL4 FILL8 FILL16 FILL32} -prefix filler_cells

How to add DECAP cells

############### adding decap cells #########################

1. addDeCapCellCandidates {DECAP10 0.019 DECAP2 0.0006 DECAP3 0.003 DECAP4 0.005 DECAP5 0.007 DECAP6 0.0102 DECAP8 0.0149 DECAP9 0.017 DECAP7 0.012}
2. addDeCap -totCap 0.800 -cells DECAP10 DECAP8 DECAP4 DECAP6 DECAP3 DECAP5 DECAP9 DECAP7 -prefix DEcap

############### adding filler cells############################

• addFiller -cell {FILL1 FILL2 FILL4 FILL8 FILL16 FILL32} -prefix filler_cells

############## Adding Metal fills ##############################

• setMetalFill -maxDensity based_on_node -minDensity based_on_node -layer {Metal1 Metal2 Metal3 Metal4 Metal5 Metal6 Metal7 Metal 8 Metal9} 
• addMetalFill -layer {Metal1 Metal2 Matel3 Metal4 Metal5 Metal6 Metal7 } -timingAware sta -net {VSS}

################# dumping pnr outs ##########################

• saveDesign  design_name.enc
• defOut -floorplan -scanChain -netlist -routing design_name.def
• saveNetlist design_name.v
• setExtractRCMode -engine postRoute -effortLevel low
• extractRC
• rcOut  -rc_corner rc_min  -spef design_name.Min_spef
• rcOut  -rc_corner rc_max  -spef design_name.Max_spef
• write_sdc  > design_name.sdc
• streamOut design_name.gds -mapFile "respective node layermap" -merge "respective node stdcell gds" -mode all -structureName design_name_top -units 2000

dbGet Commands

1). To report the number of inputs 

• dbGet top.numInputs 

2).To report the number of instances

• dbGet top.numInsts

3). To report the status of the design

• dbGet top.statusRouted
• dbGet top.statusIoPlaced
• dbGet top.statusClockSynthesized

4). To get the properties of the selected objects

• dbGet selected.??

5). To get the instances names for the particular cell

• dbGet top.insts.cell.name BUFX2* -u

6). To get the cell name of the particular instance

• dbGet [dbGet -p top.insts.name instancename].cell.name

7). The selected net is clock net or not

• dbGet -p1 top.nets.isCtsclock 1

8).  To get the dont touch attributes

• dbGet top.insts.isDontTouch 1

9). To report the power domain names

• dbGet top.fplan.groups.pd.name

10). To check the fixed status of the cell

• dbGet [dbGet -p2 [dbGet -p top.instspStatus fixed].cell.name invx1]

11).To report the core box

• dbGet top.fplan.coreBox

12).  To report the placement blockage area

• dbGet top.fplan.pBlkgs.area

13).  To report the sequential cells

• dbGet [dbGet -p2 top.insts.cell.isSequential 1].name
• dbGet [dbGet -p2 top.insts.cell.isSequential 0].name

14). To report the net name which is connected to pin

• dbGet [dbGet -p top.insts.instTerms.name pinname].net.name

15). To report the status of your design

• dbGet top.?? status*

16). To report the layers max_min density issues

• dbGet head.layers.maxDensity
• dbGet head.layers.minDensity

17). To report the minspacing 

• dbGet head.layers.minSpacing
• dbGet head.layers.minWidth

18). To report the vias name

• dbGet head.vias.name

19). To report the manufacturing grid

dbGet head.mfgGrid

20). To report the macro cells in the design

dbGet [dbGet -p1 top.insts.cell.subClass block].name

21). find the net name which is connected with a particular pin

• dbGet [dbGet top.insts.instTerms.name pin_name -p].net.name
•  dbGet [dbGet top.insts.instTerms.name  pin_name -p].isOutput
•  dbGet [dbGet top.insts.instTerms.name  pin_name -p].isInput  
• dbGet [dbGet [dbGet top.insts.instTerms.name  pin_name -p].layer].name (which metal layer is connecting to that pin)
• dbGet [dbGet top.insts.instTerms.name  pin_name -p].dontTouch