Synthesis

Synthesis

Tools used: Genus/RC compailer
What is Synthesis

• Synthesis is a process of converting RTL code to Gate_level_netlist is called synthesis

Why Synthesis:

• To manufacture the behavioral code ,so we are converting to Gate level netlist

Inputs to Synthesis 

• Libraries
• SDC
• RTL code (synthesizable)
• technology File
• Lef file

Outputs of Synthesis

• Synthesized SDC 
• Synthesized Netlist (.v)

Goals of Synthesis

• To get a gate level Netlist
• Inserting clock gates
• Logic optimization
• Inserting DFT logic
• Logic equivalence between RTL 
• The area will decide (area got reduced by doing the optimization)
• Gate count will decide (based on the logic and optimization process)

create a File with the name of flist we will include the all the Verilog netlists like top module sub-module netlists the below web address do point out the flist file

https://nagarajuphysicaldesign.blogspot.com/2019/11/flist.html

create one sdc file and you can define the clock in that file at clock port like
create_clock -name clk -period 10 -waveform {0 5}  [get_ports clock_port name}
the below path will address the sdc file

https://nagarajuphysicaldesign.blogspot.com/2019/11/synopsis-design-constrains.html

> genus -f scripts

after the synthesis it will provide the synthesized netlist, we will do the sanity checks in Genus for timing as well as design-related checks

1. Check_timing
2. Check_design 

• In flist file keep top-level netlist first and run the synthesis 
• genus provides the unresolved references for sub-modules which are defined in Top-level netlist
• 100% genus will provide the unresolved reference for all submodules which are defined in top module 
• If genus doesn't provide the unresolved references for specific submodule please check the netlist, if is there any ifdef statements are presented or not
• If the top-level netlist has ifdef statement is defined before for that particular submodule genus won't provide the unresolved references for that submodule you can define the ifdef statement name in scripts file by the following command
• read_hdl -f flist -define {"abcd" "efgh"}  
• If you get the unresolved references in the design you can include that module netlist in the flist file and re_run the synthesis until to clear the unresolved references.
• If your design has more flops you can create the block boxes 
• first, check for a two-dimensional array (2D_register) are there  in Verilog netlists, in netlist path, if the register count is more than two hundred  you can create it as a block box
• You can create an empty module for that and include in flist and rerun the synthesis, and it provides the empty module
• this empty module consists of the only module, instance name input-output and inout information it does not has any information 

Process of Synthesis

1. Translation
2. Mapping
3. Optimization

• If your design has constants you can remove by placing the buffers without any optimization

llength [get_db ports -if {.direction==in}]
llength[ [get_db ports -if {.direction==out}]
report_timing -lint .... will give the unconstrained path details

1. Translation:

• Process of converting behavioral code to generic Boolean algebra, It is a technology independent
• For Gtech library we don't have timing inforamtion

2. Mapping

• Selecting the suitable cell from the Technology library it is technology dependent based on input tool will pick the suitable cell from the lib

3. Optimization:

• Optimize the logic ,it will remove the  redundancy logic will be deleted
• Tool will optimize for the area power and performance.

4. Empty module:

• It has only inputs and outputs information, it doesn't have any logic inside the module definition.

5.Unresolved references

• Module definition is present but timing library is missing is called unresolved references 

6.Block_Box

• Macros are block boxes ,there is no functional information but it has timing info 

7.Elaborate:

• Translate the design into its GTECH representation
• Allows changing the parameters values defined in the source code replace the HDL arithmetical operators in the code with the design ware component
• It will check for the sub modules in the Top module ,if there are any gate-level netlists read in with the RTL files, Genus automatically links the cells to their references in the technology library during elaboration.
• It links the design automatically

8).link:  It will link the Design

9). what happens during optimization techniques

• Path adjustment
• Path grouping
• Re-timing
• Tns optimization
• Ungrouping

10). What are the different stages of Optimization in synthesis

• Architectural optimization
• Sharing the sub expressions
• Sharing the resources
• Selecting the design ware components
• After completion of this optimization  design is represented GTECH format
• Logical optimization 
• Will do Boolean algebraic optimization
• Gate level Optimization
• During this stage the logic is converted to logical gate level netlist
• Incremental optimization
• redundancy logic will converted to equivalent gate

11). What is retiming

• Retiming is an advanced optimization technique where registers are re-positioned to reduce cycle time or area without changing the input-output latency of the design. 
• This technique is best fitted for a design that can be pipe lined. 
• The drawback of this technique is, possible problem in formal verification.
• Retiming can be enabled at the top level or selective modules using the ‘retime’ attribute.
• Retiming can recover sequential area from a design with both easy to meet timing goals and a positive slack from the initial synthesis.
• Retiming a design that does not meet timing goals after the initial synthesis could impact total negative slack: the paths with the better slack can be “slowed down” to the range of worst negative slack

12).Path Adjust

• Tightening the constraint on a selective path will make the path become more critical and force Genus to work harder on it. 
• This trick can help closing timing for a small number of violating paths. 
• The following constraint needs to be set before mapping
• path_adjust -delay <> -from -to 

6).Boundary Optimization:

• Propagation of constant across the boundary
• Propagation of equal and opposite information across the hierarchy
• propagation of unconnected Port information across hierarchy
• Pushing of inverters across the hierarchy

13).Ungrouping :

• ungrouping merges the sub design of a given hierarchy into the parent cell or design ,it removers the hierarchical boundaries and allows design compiler to improve the timing by reducing the levels of logic and to improve the area and sharing logic

Few commands :

• check_timing_intent
• checkDesign -all

https://www.blogger.com/blog/post/edit/7948084828664881049/3698505313912971628#