Basics Of Semiconductor

 Semiconductors

Semiconductor : It is nothing but partially conducting the electricity is nothing but Semiconductor.

• Semiconductors are classified into two types
• Intrinsic Semiconductor
• Extrinsic Semiconductor

Intrinsic Semiconductor :

• Purist form of the Material is nothing but Intrinsic Semiconductors

Extrinsic Semiconductor :

• Impurities are added to conduct the electricity is called Extrinsic Semiconductor
• Types of Extrinsic semiconductors are divided into two types 
• P type semiconductor
• N type semiconductor
• P type Semiconductor : Trivalent impurities are added to the tetra valence material is called as P type Semiconductors ((4th group element)Si+(3rd group element)Boron
• N type semiconductor : Penta valent impurities are added to the tetra valence material is called as N type Semiconductors ((4th group element)Si+(5th group element)Phosphorous

Doping : It is nothing but the addition of the impurities to the material is called as the Doping 

Dopands are tri and penta valenmt elements

Why silicon ? Why not Germanium

 Why Silicon ?

• low leakage current
• More energy band gap  (1.21eV for 0K, 1.1eV for 300k)
• More resistivity Approximately 231.5 k ohm centimeter
• Mobility of the electron is 1300 sq cm /Volts
• Mobility of the Hole is 500 sq cm /Volts
• More resistance
• High Temperature 1425 degree centegrade

Basics of the Electronic devices

Atom: Atom is nothing but a smallest tiny particle of a chemical element,it can't be divisible further is called as Atom

Nucleus : A nucleus is the positively charged center of the atom consisting if proton and neutrons is called nucleus

• Electron: A negatively charged particle is nothing but electron
• Electron is discovered by JJ Thomson (1897)
• Charge electron is -1.6*10^-19 eV
• Proton : A Positively charged particle is nothing but proton it has same magnitude of electron charge 1.6*10^-19eV
• Neutron : There is no charge on the Particle 

Voltage: The Potential difference between the two ends of the conductor is called Voltage (Units are Volts (V))

Current : The time taken by the charge to posses through the cross sectional area of a conductor is called as Current 

• Current is indicated with i
• Units of Ampere

Power : The Product of voltage and current is nothing but Power

• P=VI (Volt-Ampere (Watts))
• Power indicated with P

Conductor : The Conductor is a material it allow the electricity is nothing but Conductor.

Examples: Cu, Fe, Al

Insulator : It doesn't allow the electricity is called insulator

Examples: wood

Semiconductor : It is a semi Conductor some times it acts has a insulator and some times a ts as a Conductor based on the requirement is called semiconductor

Examples : Si, Ge

Clock gating checks

 Clock Gating checks:

A gated clock signal occurs when the clock network contains logic of AND/NAND/NOR/OR

consider a AND gate ,it has two inputs (Enable pin and clock pin)and one gated output clock

• If Enable Pin logic 1 gated output clock is equals to input clock
• If Enable pin logic is 0 gated output clock is equals to zero
• will check the clock gating setup and hold time checks at lower state of the clocks for NAND and AND gate ICG cells
• will check the clock gating setup and hold time checks at upper state of the clocks for NOR and OR gate ICG cells

to obtain the proper gate clock checks we must satisfies the following conditions

• Control input Enable is must satisfies setup check and hold check
• Clock input must have controlling state
• setup checks will ensure the leading edge of the clock must be stable before the active clock edge
• hold check will ensure the trailing edge of the clock must be stable after the active clock edge
• If enable changing in non controlling state it may cause timing violations otherwise no violations

How to dump the reports

   Sanity checks related Commands

• checkFplan -reportUtil > ./reports/dir/utilization.rpt
• checkPlace  > ./reports/dir/checkPlace.rpt
• check_timing -verbose > ./reports/dir/check_timing.rpt
• checkNetlist > ./reports/dir/check_netlist.rpt
• checkDesign -all > ./reports/dir/check_design.rpt
• checkUnique > ./reports/dir/check_unique.rpt

Congestion Report

• reportCongestion -overFlow > ./reports/dir/congestion.rpt
• reportCongestion -hotspot > ./reports/dir/congestion1.rpt

Timing Reports

• report_timing -max_paths 100 -early > ./reports/dir/early.rpt
• report_timing -max_paths 100 -late > ./reports/dir/late.rpt
• report_constraints -all_violators -drc_violation max_transition  > ./reports/dir/max_transition.rpt
• report_constraints -all_violators -drc_violation max_capacitance  > ./reports/dir/max_cap.rpt
• report_constraints -all_violators -drc_violation max_fanout  > ./reports/dir/max_fanout.rpt
• timeDesign > ./reports/dir/timeDesign.rpt

Skew Reports

• report_clock_timing -type skew -early -clock clock_name >./reports/dir/early_skew.rpt
• report_clock_timing -type skew -late-clock clock_name >./reports/dir/late_skew.rpt
• report_clock_timing -type summery -clock clock_name >./reports/dir/skew_summary.rpt

Gate_count

• reportGateCount > ./reports/dir/gate_count.rpt
• report_power > ./reports/dir/power.rpt

How to use Dont _touch and Dont_use Attributes

• set_dont_use [get_lib_cells *CLKBUFF*] true
• set_dont_use [get_lib_cells *CLKINV*] true
• set_dont_use [get_lib_cells *CLKMUX*] true
• set_dont_use [get_lib_cells */*LVT] true
• set_dont_use [get_lib_cells */*HVT] true

 

How to generate the PnR outputs (In innovus)

• saveDesign  Dbname.enc
• defOut  -floorPlan -scanChain -netlist -routing dbName.def
• saveNetlist dbName.v
• extractRC
• rcOut -spef spef.name -corner <corner_Name>
• streamOut design_name.gds -library lib_name -map stramOut.map

How to edit the pin placement at floor plan stage

editPin -pinWidth 0.1 -pinDepth 0.1 -fixOverlap 1 -unit MICRON -spreadDirection clockwise -side Left -layer 1 -spreadType center -spacing 0.2 -pin {ab/a ud/b} 

Note: Layer Number ,PinWidth ,Pindepth , Spacing is based on Top level

Global Net Connections

How to Apply the Global net connections

• globalNetConnect pwr -type pgpin -pin VDD
• globalNetConnect  gnd -type pgpin -pin VDD
• globalNetConnect VDD -type pgpin -pin VDD
• globalNetConnect VSS -type pgpin -pin VSS
• applyGlobalNets

 

How to fix DRVs at cts stage

set_ccopt_mode -cts_opt_type cluster
it will fix the drv violations but it wont balance the skew
set_ccopt_mode -cts_opt_type full
it will balance the skew

Interview Questions Part 2

1. Timing Optimization at Synthesis

• Timing optimization will reduce the gate count 
• Timing optimization will remove the redundancy logic and place AOI or AIO logic

2. Explain About UPF

• It is a Uniformed Power factor for POWER
• In this file will define about Low Power cells strategy
• Defining the scope for the module
• Defining the Power Domains
• creating the supply nets
• Creating the Power switch strategy

3. Challenges faced in your Project at synthesis

1. Check_timing Issues

• Input Delay Assertion
• Output Delay Assertion
• External Load Assertion
• Unconstrained End Point
• Combinational Loops
• Generated clocks
• Driving cell Assertion

    2.Check_Design issues

• Unresolved References
• multi Driven nets
• Constants
• Floating nets

4. How do -max_paths and -nworst  work in report_timing  command

• yes it will work
• max_paths it will give the maximum number of paths which are failed it will report based on the number
• nworst means many start points but only one end point is called nworst

5. What is re-timing in synthesis

• where registers are re-positioned to reduce the cycle time or area without affecting the latencies
• Re-timing works by moving , splitting or merging registers through the cones of the logic

6. Explain about setup and hold time

• Setup time: The minimum amount of time the data could be stable before active clock edge is called setup time
• Hold time : The minimum amount of time , the data could be stable after the active clock edge is called hold time

7. What is the difference between Flop and Latch

• Flop is a edge triggered ,Latch is Level sensitive
• Dynamic Power Consumption is high is flop compare to latch
• The performance is slow in Flop compare to Latch because only one half cycle is required to data received 
• Noise in flop is less compared to latch because flop is edge triggered and latch is level sensitive

8. Time borrowing

• Maximum Time borrowing  is nothing but width-setup time allowable time barrowing
• Data can arrive later than capture clock arrival and borrow from the next clock cycle this called Time borrowing

9. why is the driving cell is used

• Basically buffer is used as a driving cell
• For better transition time 

10. Explain about false path

• False path is a path we don't want to do  the timing analysis for that path is called as false path, it is physically available but logically it is not available
• False path is a one of the timing constraint it will used between two clock Domains
• Consider The cascade connection  of two multiplexers it has same selection pin
• Mux inputs are A (on logic 0) and B(logic on 1) for 1st mux, Selection is SE, second mux inputs are C (Logic 0) and D (Logic 1)
• If selection SE is 0, whatever the data is available at logic 0 (A) will fed to mux 2 logic1 (D pin of the mux) , so data which is available on data on logic 0(C) of the mux 2 will go out from the output port of the mux is Y 
• here A to Y is false Path

11. What are the basic constraints to start Synthesis

• Creat_clock is the basic constraint to start synthesis

12. What is the structure of the Flop

• The back to back connections of Latch is nothing but flop

13. What happened if in your design as Combinational loops

• If your design has combination loops data is not reaching to the received flop because  it will feed back the output to input of the loop
• we will report to RTL team they will solve the issue
• set_disabling_timing -from [get_pins pin_name] -to [get_pins Pin_name]
• Breakpoints will break the feedback path in combination path in data path

14. What do you mean elaboration

• Genus automatically links the cells to their references in the technology library during the elaboration,after completion of the elaboration it will display the unresolved references names

Interview Questions Part 1

 1.Which tools are used for IR Drop Analysis

• Voltus From cadence
• Redhak from Ansis
• Prime Power From Synopsys

2.How did You fix IR Drop in you design?

• Increasing the Width of the Stripe
• Increase the number of stripes
• Use Partial Blockage
• Spread the logic by using Keep_out Margin  
• Use Decap cells
• Increase the number of Power sources

3.What was the threshold value of IR Drop

• Basically 5% of the VDD is consider for allowable Drop other wise we may is the Drop issue

4.How did You resolve the Antenna Effect

• We can reduce the antenna Violation by adding the Diode in reverse bias at Near the Gate terminal of the transistor
• Metal jumping is also one of the technique to resolve the antenna violation

5.How is Antenna Issue Causing

• While doing the CMP (Chemical Mechanical Process) Process The charge is induced in the net, the Induced charge is choosing the path to discharge,it will start discharging through the gate terminal of the Transistor ,the gate terminal may not have that much capable so it may damage 

6.Challenges faced during  your Project

• Congestion
• Macro Placement
• Set up Timing Violations And DRV Violations 

7. How you Done Manual Routing

• Yes , I have done Few Manual routing to create the stripe

8. What is the command to setting false path command

• set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
• set_false_path -through [get_cells -of_objects [get_pins cellname/D]]

9.What were the settings given for CTS

• Clock Fanout 
• Clock cells ,clock buffers,clock inverters
• Clock Skew target
• Clock Transition
• Clock Insertion delay

10. What is Cross_talk and its Effect

• When two nets of the same metal layers runs parallel and close to each other ,signal on one net is switching (Aggressor) and another signal on another net is constant at that time the switching signal may affected to non switching signal net due to coupling capacitance is called the Cross_talk
• When the switching window is matching, timing will degrade otherwise Noise will come ,that noise is depends on magnitude and width
• If Aggressor and victims both are  switching in same direction ,victim transition becomes fast resulting data to arrival early which may cause hold time violation
• If Aggressor and victim both are switching in different direction, victim net signal transition slows down which increase the delay it may violate the setup time violation 

Timing Constraints

 Input Delay constraints

60%,40% of the clock is input delay

Example:

If your clock time period is 1ns the input delay we should consider 60% of the clock so put 600ps for input delay , which the time taking the signal from the external clock definition point to the input port of your block, remaining 40% will be consider for internal logic of your block.

Output Delay constraints

30%,70% of the clock is output delay

Example

If your clock time period is 1ns ,the output delay we should consider 70 % of the clock so, you put 700ps for output delay which means , time taken by the signal reaching from output port of the block to the external flop D pin, remaining 30% of time we should consider for your block.

Load:-

The load we should consider 0.02femptofarads 

Assume By default 2 to 3 times of the NAND gate input cap 

Driving_cell:-

The thumb rule is 10% of the clock period , If it is more pessimism take 5% of the clock period

NAND gate are will decide the core area

Because the total gate count is equals to the ratio of the total cell area to NAND gate equivalent area  

DELAY CELL

 DELAY CELL

    Delay cell is used to fix the hold violation, the internal structure of the delay cell is the back to back connection of Inverters  is called Delay buffer cell, The cascade connection of two different drive strength buffers is called delay cell. 

    If the 1st cell is driving inverter drive strength is high no issues otherwise it may not have the driving capable to drive the followed inverter cell it may introduce the delay in the delay cell based on the output cap delay will incerease which means the output cap will take lot of time to charge the capacitor that's why it is introducing the delay in delay cell 

Find the flops and combinational cell

 get_db insts -if {.is_combinational == true} - to return all the combinational cells

get_db insts -if {.is_sequential == true} - to return all the sequential cells

ECO_Fixes

 ################ Eco fixes #######################################

write_eco_opt_design

set_eco_opt_mode -load_eco_opt_db ecoTimingDB/

eco_opt_design -drv

dmmmc> set_eco_opt_mode –add_inst false

eco_opt_design -hold

################## Manual fixing ###############################

dmmmc> change_cell inst1 –upsize

dmmmc> add_repeater –term inst2/Y –cell BUFX6 

eco_opt_design –setup