Interview Questions Part 2

1. Timing Optimization at Synthesis

• Timing optimization will reduce the gate count 
• Timing optimization will remove the redundancy logic and place AOI or AIO logic

2. Explain About UPF

• It is a Uniformed Power factor for POWER
• In this file will define about Low Power cells strategy
• Defining the scope for the module
• Defining the Power Domains
• creating the supply nets
• Creating the Power switch strategy

3. Challenges faced in your Project at synthesis

1. Check_timing Issues

• Input Delay Assertion
• Output Delay Assertion
• External Load Assertion
• Unconstrained End Point
• Combinational Loops
• Generated clocks
• Driving cell Assertion

    2.Check_Design issues

• Unresolved References
• multi Driven nets
• Constants
• Floating nets

4. How do -max_paths and -nworst  work in report_timing  command

• yes it will work
• max_paths it will give the maximum number of paths which are failed it will report based on the number
• nworst means many start points but only one end point is called nworst

5. What is re-timing in synthesis

• where registers are re-positioned to reduce the cycle time or area without affecting the latencies
• Re-timing works by moving , splitting or merging registers through the cones of the logic

6. Explain about setup and hold time

• Setup time: The minimum amount of time the data could be stable before active clock edge is called setup time
• Hold time : The minimum amount of time , the data could be stable after the active clock edge is called hold time

7. What is the difference between Flop and Latch

• Flop is a edge triggered ,Latch is Level sensitive
• Dynamic Power Consumption is high is flop compare to latch
• The performance is slow in Flop compare to Latch because only one half cycle is required to data received 
• Noise in flop is less compared to latch because flop is edge triggered and latch is level sensitive

8. Time borrowing

• Maximum Time borrowing  is nothing but width-setup time allowable time barrowing
• Data can arrive later than capture clock arrival and borrow from the next clock cycle this called Time borrowing

9. why is the driving cell is used

• Basically buffer is used as a driving cell
• For better transition time 

10. Explain about false path

• False path is a path we don't want to do  the timing analysis for that path is called as false path, it is physically available but logically it is not available
• False path is a one of the timing constraint it will used between two clock Domains
• Consider The cascade connection  of two multiplexers it has same selection pin
• Mux inputs are A (on logic 0) and B(logic on 1) for 1st mux, Selection is SE, second mux inputs are C (Logic 0) and D (Logic 1)
• If selection SE is 0, whatever the data is available at logic 0 (A) will fed to mux 2 logic1 (D pin of the mux) , so data which is available on data on logic 0(C) of the mux 2 will go out from the output port of the mux is Y 
• here A to Y is false Path

11. What are the basic constraints to start Synthesis

• Creat_clock is the basic constraint to start synthesis

12. What is the structure of the Flop

• The back to back connections of Latch is nothing but flop

13. What happened if in your design as Combinational loops

• If your design has combination loops data is not reaching to the received flop because  it will feed back the output to input of the loop
• we will report to RTL team they will solve the issue
• set_disabling_timing -from [get_pins pin_name] -to [get_pins Pin_name]
• Breakpoints will break the feedback path in combination path in data path

14. What do you mean elaboration

• Genus automatically links the cells to their references in the technology library during the elaboration,after completion of the elaboration it will display the unresolved references names