Clock gating checks

 Clock Gating checks:

A gated clock signal occurs when the clock network contains logic of AND/NAND/NOR/OR

consider a AND gate ,it has two inputs (Enable pin and clock pin)and one gated output clock

• If Enable Pin logic 1 gated output clock is equals to input clock
• If Enable pin logic is 0 gated output clock is equals to zero
• will check the clock gating setup and hold time checks at lower state of the clocks for NAND and AND gate ICG cells
• will check the clock gating setup and hold time checks at upper state of the clocks for NOR and OR gate ICG cells

to obtain the proper gate clock checks we must satisfies the following conditions

• Control input Enable is must satisfies setup check and hold check
• Clock input must have controlling state
• setup checks will ensure the leading edge of the clock must be stable before the active clock edge
• hold check will ensure the trailing edge of the clock must be stable after the active clock edge
• If enable changing in non controlling state it may cause timing violations otherwise no violations