Tie cell

Tie cells

• Tie cells are the connected to the whose input is constant high/constant low we will connect the tie cell to connect the gate terminal of the transistor to either power or ground 
• In lower technology nodes, tie high and tie low cells are used to avoid the direct gate connection to the power or ground network
• If the gate terminal is connected to power/ground the transistor might be turned on/off due to voltage fluctuations in power/ground net or some time gate may damage due to high power fluctuations. so that is the reason we will connect the tie cells between power and gate terminal of the transistor.
• Tie cells are connected near to the gate terminal
• Tie hi cells are connected to VDD
• Tie lo cells are connected to VSS
• These cells are apart of std_cell library
• In Placement stage tool will place the tie cells based on fanout 

Command :

• SetTieHiLoMode -cell "TIEHI TIELO"  -maxfanout 10
• addTieHiLo -powerDomain Power domain name

After adding the Tie cells we need to apply the global nets
globalNetConnect VDD -type tiehi -pin VDD
globalNetConnect VSS -type tielo -pin VSS
applyGlobalNets

End Cap Cells and how to place end cap cells in the design

END CAP CELLS

• End cap cells are pre placed physical only cells it has only physical connectivity 
• End cap cells are placed at the end of each site row [left and right side of the row]
• These library cells don't have signal connectivity
• They connect only to the power and ground rails once power rails are created in the design
• Each end of the core row, left and right, can have only one end cap cell specified
• However, you can specify a list of different end caps for inserting horizontal end cap lines, which terminate the top and bottom boundaries of objects such as macros
• End caps have a fixed attribute and cannot be moved by optimization steps
• A core row can be fragmented (contains gaps), since rows do not intersect objects such as power domains. For this, the tool places end cap cells on both ends of the un-fragmented segment
• while doing the fabrication of the chip the corner cells may get damage it leads to functional failure to resolve this issue will place the end cap cells at the end of the site rows, in this case end cap cells are protecting to the logical cells (Std cells). 

Command:

setEndcapMode -rightEdge FILL1 -leftEdge FILL1

addEndCap -prefix endcap -preCap FILL1 -postCap FILL1 

example: If your design is multi voltage we use the following command to place the end cap cells

• addEndCap -prefix endcap -preCap FILL1 -postCap FILL1 -powerDomain PD1
• addEndCap -prefix endcap -preCap FILL1 -postCap FILL1 -powerDomain PD2

Note: FILL1 cell i consider as a EndCap cell and PD1, PD2 are power domains

Frequently Asking questions on PD

Synthesis

1. What is Synthesis
2. Which tool is using for the synthesis
3. What are the inputs and outputs of Synthesis
4. How to resolve the check_timing_intent issues in Genus
5. How did you resolve the unresolved reference issue in the genus
6. What is  "Flist" , what does it contains
7. What is RTL Code
8. what synthesis guy will do if the netlist is not good?
9. What is the wire load model?
10. what is the NLDM wire load model? When will you use the NLDM Model
11. What is the ccs wire load model? 
12. How do we reduce the Interconnect resistance
13. What is the wire load model?  Explain its classifications
14. How  to represent the  Extracted parasitics
15. what is DSPF? Explain its demerits
16. What is RSPF? Explain its disadvantages
17. What is SPEF

Physical Design

1. What are the inputs for PNR
2. In innovus which file should read first
3. What does SDC contain
4. What does .tf contains
5. While running PNR flow which file should read first?
6. Where do we get the leakage power and voltage information
7. what does netlist contains
8. What is the difference between tracks and Metal layers
9. What is CPF
10. What is Aspect Ratio
11. What is the effect of Aspect Ratio in your design
12. What is utilization
13. How do we calculate the chip utilization
14. What is you're starting utilization
15. How to decide your core Area
16. What is your Row height ?
17. What is the offset value? what is the need for offset value in your design and what is the offset value of your design?
18. What is Channel Spacing
19. How to Calculate the Channel spacing
20. How many types of  Floor plans are there? which type of floor have you done for your design
21. What is a black box
22. Where do we place the macros in your design ? on what bases did you place the macros
23. What does the meaning of Fly lines? how many types of Fly lines are there in your design
24. What is abutted  and non abutted floor plan?
25. What is the meaning of the ORIENTATION
26. What is the pitch of the Highest metal layer in your design
27. Which metal layers are blocked by the macro pins
28. How many pins are there for a one hierarchy macro family 
29. How many hierarchy's are there in your Design
30. What is the impact on your design ? if i place the macros inside the core Area
31. How many Metal Layers are there in your design
32. What is Physical cells
33. Which Physical cells are placed  in floor plan stage?
34. Why we need to use the well taps in your design
35. What is the need of END cap cells
36. What are the inputs for power plan
37. How many stripes are there in your design
38. What is stripe ,follow pin, rail,Ring
39. What is the width of the Ring
40. Which metal layers are prefers for RING and why ?  
41. Which metal layer is used for Ring and why?
42. What is set to set distance in your design
43. Which metal layers are used for stripes why?
44. What are the checks you have done after the power plan?
45. How many opens and shorts are there in your design
46. After the power plan, what is your utilization
47. What is the area of  your design
48. What is power?
49. What is a dangling net? If your design has dangling nets on how to resolve this issue
50. What is Power EM? What is Signal EM
51. What is the impact on Timing by EM violation
52. What is Antenna Effect?
53. What is IR Drop? how many types of IR Drop are there in your design?
54. What is the Impact of IR Drop on timing?
55. What is the impact of the Power EM in your Design
56. What are the disadvantages of the Signal EM
57. What is SRoute?
58. What is LEVEL SHIFTER? where do we use the Isolation cells in your design
59. What is Isolation cells? Which cells are used as Isolation cells
60. What is Retention flops? What is the need for this in your design 
61. What is always on Domain?
62. What is the switch cell?
63. What is the target IR drop in your domain
64. How many power domains are there in your domain
65. What is the placement?
66. What is placement flow?
67. What is SCAN DEF
68. What does Scan def contains
69. What are the checks have you done on after the placement
70. What is Congestion 
71. What are the different Techniques have you used to reduce the Congestion
72. Where did you observe the congestion in your design
73. What is Cell padding
74. After applying the Cell padding what kind of issue will come
75. What is the difference between Module padding and  instance padding
76. After applying the Cell Padding what is the impact on your design
77. Why padding is required?
78. What is pin density?
79. Due to which cells did you get the Pin density
80. What is cell Density
81. What is the density ? after the placement of the design
82. What is Tie cell? 
83. What is the need to tie cell 
84. Where do we place the tie cells and what is the fanout of the Tie cell in your design
85. Which cell is there in the Congestion Hot spot.
86. Which timing checks we will do after the placement
87. Why hold time is not considered at the placement stage
88. What is the difference SCAN FLOP and Normal Flop
89. If I am unable to meet the timing what should I do? at the placement stage?
90. If I insert a buffer in test mode will it impact functional mode? 
91. What you do in Test mode for timing?
92. What you did in test mode for timing closure?
93. What are the violations you see in test mode?
94. How to fix the SETUP violations
95. How to fix the Hold violations
96. How to fix the DRC Violations
97. How to fix the Transition violations
98. How to fix the Max cap violations
99. While fixing the cap violation where do we add the Buffer
100. What is the typical Buffer delay?
101. What is the typical Delay cell delay?
102. What is Scan chain reordering?
103. What is the impact on design after scan chain reordering
104. What is the difference between the Clock buffer and Normal buffer
105. What is Transition in STA point of view
106. Will you route the signal route without CTS? 
107. What does DEF contains
108. What are the inputs and outputs of clock tree synthesis
109. Which cells are used to build the clock tree and why
110. If i use only clock inverters to build the clock tree what is the impact on the design
111. If i use only clock buffers to build the clock tree what is the impact on the design
112. If i use both clock inverters and clock buffers what is the impact on design
113. What is CTS spec
114. What does CTS spec file contains
115. Why Clock tree synthesis is required
116. What are the Objects of clock tree synthesis
117. What is insertion Delay?
118. Which Metal layer is used for clock route
119. In which corner did you build the corner?
120. Why clock uncertainty is specified for a clock?
121. If you design have more skew what is the impact on you are design
122. If insertion delay is more what will happens in your design?
123. What is skew balancing
124. What is use_full skew? where do we add the useful skew in your design
125. What is cross talk? how to control the cross-talk
126. Cross talk fixing techniques?
127. What is cross talk noise? how to reduce the cross talk noise
128. What is cross talk delay 
129. what is the output of the cross-talk tool
130. What is the Min Pulse Width violation? how to resolve these violations
131. Why min pulse width violation will cause? 
132. On which path min pulse width violation will cause? and why?
133. What is the importance of the transition?
134. What are the extracting tools do we have?
135. Define

• skew
• slack
• uncertainty
• jitters
• transition
• slew
• cross-talk
• arrival time
• required time
• latency
• capacitance
• input delay
• output delay
• setup time
• hold time
• recovery time
• removal time
• multi-cycle paths
• false paths
• half cycle paths

SED COMMANDS

SED COMMANDS

Insert a blank line after each line /Insert two blank lines

• sed G filename.txt
• sed 'G;G' filename.txt

Delete the blank lines

• sed '/^$/d' filename.txt

Insert 5 spaces to the left of every lines

• sed 's/^/     /' filename.txt

To delete the particular line

• sed '10d' filename.txt

To delete the lines range from p to q

• sed '5,10d' filename.txt

To delete nth to end line

• sed '10,$d' filename.txt

To delete the matched pattern

• sed '/Nagaraju/d' filename.txt

To delete the lines which matches the pattern and 5 lines after to that pattern

• sed '/Nagaraju/,+5d' filename.txt 

To print the lines range from 10 to 50 of the file

• sed -n '10,50p' filename.txt

To print the lines except that range from 5 to 10

• sed -n '5,10d' filename.txt

To print the particular line and to print the lines from 5 to end of the line

• sed -n '10p' filename.txt
• sed -m '5,$p' filename.txt

To print the line which matches the pattern

• sed -n /Nagaraju/p filename.txt

To prints lines from the nth line of the input ,up to that line matches the pattern ,if the pattern lines doesn't found then it print up to the end of the file

• sed -n '1,/Nagaraju/p' filename.txt

To replace the pattern matches in the entire file with g without g current position of the line

• sed 's/Raju/Nagaraju/g' filename.txt

To replacing the nth occurrence of the pattern

• sed 's/Raju/Nagaraju/2' filename.txt

To replacing pattern on a specific line number 

• sed '10 s/Raju/Nagaraju/' filename.txt

To replacing the pattern on a defined range and ignoring the case

• sed '10,20 s/Raju/Nagaraju/i' filename.txt

Replace one pattern followed by the another pattern

• sed '/is/ s/Raju/Nagaraju/' filename.txt

Replace a pattern with other except in the nth line

• sed -i '5!s/Raju/Nagaraju/' filename.txt

How to displace the alternative line

• sed -n '1~2p' filename.txt

How to print pattern1 to pattern 2

• sed -n '/pattern1/,//pattern2/p' filename.txt 

Tar the file
tar -cvf filename.tar filename
Untar the file
tar -xvf filename.tar

GREP COMMANDS

GREP COMMANDS

To search the pattern in a particular file

• grep "Nagaraju" filename.txt

To search a pattern without case insensitive

• grep -wi "nagaraju" filename.txt

To search a pattern before and after the 10  lines

• grep -win -A/B/C 10 "Nagaraju"   filename.txt

To display all file names which contains the searched pattern

• grep -win "Nagaraju"  ./* 

To display other than that the searched pattern

• grep   -v "Nagaraju" filename.txt
• grep   -vE  "pattern1|pattern2" filename.txt

Displaying the count of the number of matches

• grep  -c "Nagaraju"  filename.txt  

To check for the whole words in a file

• grep -w "Nagaraju" filename.txt

To show the line numbers of the matched pattern

• grep -n "Nagaraju" filename.txt

To Display the matched pattern

• grep -o "Nagaraju"  filename.txt

To display the matching pattern that starts/ends with a string

• grep "^Nagaraju" filename.txt
• grep "Nagaraju$" filename.txt

How to grep multiple 

• grep -E "Naga|Raju" filename.txt

GVIM EDITOR

GVIM EDITOR

In Gvim Editor we have three modes 

• Command mode
• Insert mode
• Visual mode

i                            Insert mode
ESC                     Command mode
yy                         Copy
10yy                     To copy 10 lines
p                           Paste
dd                         Delete
10dd                     To delete 10 lines
u                            Undo
J                             Joint back the line
gf                           to the file
:bd                          Back to the file
:vsp                       Vertical split
:sp                         Horizontal split
ctrl+ww                To go the next file
ctrl+a                   Increasing the number 

ctrl+x                   Decreasing the number

:wq!                      Save and close
a                            Insert mode after the  cursor
shift+a                  Insert mode at the end of line
/pattern                Search the pattern
:$                           Cursor will to the last line
:~                           Converting from lower case to upper case
:R                          Replace the file name
:csh                       Entering into Linux shell
gg                          To go to the top of the file
shift+gg                To go to end of the file
100 gg                   To got to 100 line
:set nu                   To set/ Enable the line numbers to view
:set nonu                 To Hide the line numbers /disable the line no view
?                             Back search
^                              It indicate the begging of the line
$                              It indicates the ending of the line
:n                             To move the nth line from current line
h                            To back side of the current cursor position
l                              To go to right of the current cursor position
j                             To go to Down line  of the current cursor position line
k                             To go to the up side of the current position line
:123,321s/old name/new name       To change the old name by new name from starting number(123) to ending number (321)

Ctrl +v    visual mode

Shift+i  and select the number of lines to insert the pattern  at the begging of the lines
write the pattern 
ESC
:s/old name/new name/gc          To change the pattern in the current cursor Position
:%S/old name/new name/g    It will change the every occurrence of the old name by new name    
:%S/$/old pattern/new pattern/gc To replace the new pattern at the end of the lines in a file
:%S/^/raju/gc                               Add raju in beginning of all the lines
:g//d    This will delete the lines wich contains previous searched pattern
:g!//d   This will deletes the other lines which doesn't contains previous pattern
:g/^$/d to delete the empty lines

:%s///n  -->if you search for a pattern in a file  that pattern will highlight, how many times that pattern was there that info it will give (count number)  
:%s/\  /\r/g  it will show one by one line

ctrl+v GJJ to combined all lines to single

%s/\n/pattern\r/g : to print the pattern at the end of the line

:n to examine the file , quickly open and close

:tabnew filename

:%S/\n/pattern\r/g to print the pattern at the end of the every line

:12 , 40 w filename.txt saved it in the file from 12 to 40 lines

:e to update the log file

:args to know the name of the file which we are opened 

:1s/\//\\\//gc   --> to replace the / with \/

:2s/_pattern_/\//gc 

:54 r filename.txt from line number 54 it will replace current file content with the filename.txt data

:g:pattern:d  if the pattern is matched on a line it will delete

:e# , (ctrl+6 or bd) back to directory

:ls ${cwd}/*  it will give the path 

readlink -f file name it will give the abspath

Sanity Checks

Sanity Checks:
sanity checks qualify the netlist in terms of timing ,checks the issues related to library files and constraints file etc.
Techniques to resolve the sanity checks and its clear explanation

1. Check_timing -verbose
2. CheckDesign -all
3. Check_library
4. Check_legality
5. Check_Netlist
6. Report_qor
7. Report_timing

1.Check_timing:

Check_timing will checks the below following Issues

• Clock wave form not reaching to the  flops
• Combinational loops
• Clock is expected but clock is not reaching to the flops/unconstrained paths
• No drive assertion
• No external input delay on the specified ports
• No external output delay on the specified Ports
• Unconstrained signal arriving at end points/ports
• Ideal clocks
• Multi_driven_nets 

Issues clear Explanation and resolve techniques
Clock wave form not reaching to the  flops:

• It means clock is not yet created ,so we will create a new clock to resolve this issues
• create_clock -name CLK -period 10 -waveform {0 5} -source [get_ports clock_port]

Combinational loops:

• A combinational loop is formed when a signal can reach back to itself without encountering any sequential device along the path.
• This loop should be broken for timing analysis, you can manually choose which segment to disable and explicitly let the timing analysis tool know.so that any meaning full path is not excluded from the timing analysis.
• By default innovus/tempus  tool will identify the combinational loop in the design and breaks the loop  at different arbitrary point.
• set_disable_timing -from A -to Y [get_cells cell_name]

Clock is expected but clock is not reaching to the flops/unconstrained paths:

• unconstrained paths means clock reaching but waveform is not reaching to the that flop D pin

Why proper clock wave form is not reaching to the reference pin/port

reasons are follows

1. If there is a case analysis
2. Disablement the timing arc
3. set_clock_sense 

• we can check for that pin whether the clock is reaching to the flop or not by following command
• get_property [get_pins Reg/D] clock_sources
• get_property [get_pins abcd/ck] clocks
• find all fan in to that flop

foreach_in_collection a [all_fanin -to  Reg/ck] {
set b [get_object_name $a]
puts "$b"
}

• select any one of the q pin and generate the clock to resolve this issue
• find the clock sources to the selected flop and where the clock sources is same then for that master clock you can create the generated clock to resolve the issue 
• create_generated_clock -name G_CLK -divided_by 2 -source CLK [get_pins reg/Q]

No external input delay on the specified ports:

By setting the input delay to that port, to resolve the issue

• set_input_delay -max 3 -clock CLK [get_ports port_name] {30% of the clock period}
• set_input_delay -min 2 -clock CLK [get_ports port_name] {30% of the clock period}

No external output delay on the specified Ports
Unconstrained signal arriving at end points/ports

If no external output delay issue is on pin you can create the generated clock or it is on the port you can give the output delay constraints

• set_output_delay -max 7 -clock CLK [get_ports port_name] {70% of the clock period}
• set_output_delay -min5 -clock CLK [get_ports port_name] {70% of the clock period}

No drive assertion

• It means no drive is specified for ports we will get this issues
• set_driving_cell -lib_cell BUFX2  [get_ports port_name]
• instead of specifying the driving cell command at input pin/port you can give the set_input_transition command to resolve this violations

Ideal Clock 
set_propagated [get_clocks all_clocks]

PD interview Questions part 3

1).What is core utilization?

• It is the ratio of (std cell area + macro area + blockage area) / total area
• Get_utilization

2).What is cell utilization?

• It is the ratio of std cell area/ total area allocated to standard cells

3).What is gate count?

• Gate count is 3 to 4 times of instance count.
• Total place-able instance area / 2 input NAND gate area in .lib
• Report_qor
• Check_physical_design  -design_statistics

4).What is aspect ratio?

• It is the ratio of vertical routing resources to the horizontal routing resources.

5).What is a channel?

• It is the minimum spacing required between two macros or between macros and boundary.

6).How do you calculate the channel width?

• Based on the fly-line analysis we will able to know the no. of signals passing through the channel and suppose “21” signals are passing than “21” metal routes are required.So if the signals are need to be routed vertically than we divide the no of routes by no of vertical layers. Suppose no of vertical layers is “3”.
• On each metal layer 7 track are needed so the width of channel should be equal to 7 tracks.

7).How do you measure the no. of signals passing through a channel?

• Through the fly-line analysis

8).How do you calculate the metal routes that can be passed through a channel?

• The no of metal routes required is equal to the no of signal passing through the channel

9).Guidelines for general macro placement?

• If two communicating macros placed close to each another and if all the pins of both the macros are connected to each other than there is no need of spacing but if some pins are connecting  with the core logic than we need to provide some spacing so that from the pin route should come and connect to the logic.
• So minimum spacing required between the 2 macros or boundary and macro is called as the channel.

10).What is Grid? Different kinds of Grid?

• Grids can be of manufacturing grid, placement grid and routing grid. The minimum metal length that can be manufactured is called manufacturing grid.
• Placement grid is nothing but one SITE whose height is equal to the STD cell height and width is multiple of M2 pitch and all the cells are placed according to this grid. During routing tool divides entire area into small square boxes and assigns horizontal and vertical tracks to it and route according to these routing grids.

11). what is core area?

• The area in which standard cells, memories, blockages, power mesh, routing of nets are present we call it as core area

12) What do you mean ny a 9Track Cells?

• If there are 9 parallel routing tracks are present in a cell than we call it as 9 track cells.

13).Typical Metal layers used in Macro?

• Generally M1 to M4 metal layers are used by macro

Floor plan Steps

Steps in Floorplan

• Initialize with Chip & Core Aspect Ratio (AR)
• Initialize with Core Utilization
• Initialize Row Configuration & Cell Orientation
• Provide the Core to Pad/ IO spacing (Core to IO clearance)
• Pins/ Pads Placement
• Macro Placement by Fly-line Analysis
• Macro Placement requirements are also need to consider
• Blockage Management (Placement/ Routing)

Spacing between Macro:

Pitch of the highest metal layer it is blocked by the  macro pin  * Total no.of pins associated with the macros

=     ------------------------------------------------------------------------

         Total No of available Metal layers in one direction

Issues arises due to bad Floorplan

• Congestion near Macro Pins/ Corners due to insufficient Placement Blockage
• Std. Cell placement in narrow channels led to Congestion
• Macros of same partition which are placed far apart can cause Timing Violation

PnR Inputs

Physical Design Inputs

1. Netlist (.V)
2. Synopsys design constraints (.SDC)
3. Libraries (.libs)
4. LEF (Library Exchange Format .lef)
5. Technology File (.tf)
6. TLU+ file

Netlist (.V) 
Synthesis team will provide .V file

It is the combination of the sequential and combinational cells and its connectivity

it contains 

• Module
• Module Information
• Cell & Instance name
• Drive strength
• Inputs
• Outputs
• Wire Information
• Hierarchy Information
• Sub-Module Names 
• Cell Library Information

Synopsys design constraints (.SDC) 
Synthesis team will provide .SDC file

• Clock Definitions
• Clock Names
• Generated Clock Names
• Operating Conditions
• Input and Output delays
• Max and Min delays
• Max_transition
• Multicycle paths
• False paths
• Set_driving_cells
• Set_drive
• Set_load
• Set_disable_timing
• Case Analysis
• Clock_uncertainty

Example SDC File:
create_clock  -name SYS_CLK -period 10 -waveform {0 0.5} [get_ports PORT_NAME]
create_generated_clock  -name GEN_SYS_CLK -source PORT_NAME  -divide_by 2 
create_clock -name V_SYS_CLK -period 10 -waveform {0 5}

set_input_delay -max 3 -clock SYS_CLK [get_ports port_name]

set_output_delay -max 7 -clock SYS_CLK [get_ports port_name]

set_max/min_delay -max 3 -clock SYS_CLK [get_pins Pin_name]
set_multicycle_path -setup 3 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_multicycle_path -hold 2 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_driving_cell -lib_cell BUFX2  [get_ports Port_name]
set_load 0.9 [get_ports out[10]]

set_case_analysis 1 [get_ports SE]

set_case_analysis 0 [get_port TM]

set_dont_use [get_lib_cells RAM2P_128x16_ss_1v08_125c_syn/RAM2P_128x16]

set_propagated_clocks [get_clocks*]

set_disable_timing [get_cells cell_name]

set_clock_uncertainty 0.250 -setup [get_clocks CLK]
set_clock_uncertainty 0.100 -hold [get_clocks CLK]
set_max_delay 5.0 [get_ports port_name]
set_load 2 [get_ports port_name]
set_input_transition 1.0 -clock clk [get_ports port_name]

Libraries (.libs):
Vendor will provide Libraries

Cell Delay = based on input transition and output load

• Setup time
• Hold time
• Removal time
• Recovery time
• Leakage Power
• Dynamic Power
• Delay
• PVT conditions
• Wire load models
• Std.lib
• Macro.lib
• IO lib
• Arcs

LEF (Library Exchange Format(.lef)):

• Std.cell LEF
• Macro LEF
• IO Lef

LEF Contains

• Cell
• Cell name
• Shape
• Size
• Orientation
• Class
• Pin Name
• Port Name
• Layout Geometries
• Blockage
• Antenna Diff Area

Technology File (.tf)

Fab Team will provide the Technology File
Technology file (.tf) in Synopsys Format
Tech_lef in Cadence Format
Technology file contains

• Units
• Mask Name
• Max current density
• Metals 
• Layers
• Vias
• Min width
• Min space
• Pitch
• Lines
• Patterns
• Intensity
• Metal Density
• Antenna Rules
• Width 
• Height
• blink

TLU + File
TLU + File  in Synopsys Format
CapTables in Cadence Format 

• Normal Captable File in 2D format
• Expanded Captable File in 3D format

Tlu+ file contains the RC coefficients 

1. TLU+ Maximum File
• It has Maximum RC values
2. TLU+ Minimum File
• It has Minimum RC values
3. Mapped File
• Mapped file maps the technology file and .itf file for Deriving the RC values

ITF (Interconnect Technology File):

• It describes the thickness and the physical attributes of conductor and dielectric used to extract the RC values for the chip

What are all floor Plan Controlling Parameters

• Aspect Ratio
• Utilization
• IO clearance

Aspect Ratio : It is defined as the Ratio of vertical routing resources to the horizontal routing resources is Called as Aspect Ratio

• If Aspect ratio is more than one (AR>1) The block shape is Vertical Rectangle which means height is more than the width
• If Aspect ratio is lesser than one (AR<1) The block shape is Horizontal Rectangle which means width is more than the height
• If aspect ratio is equals to one the block shape is SQUARE 

Utilization :

• Area of the core that is used by placed Standard Cells and Macros expressed in percentage

IO clearence:

• The spacing between the core boundary to die boundary is called as IO clearance

Commands Used in Floorplan (ICC TOOL)

• How to know the Utilization of the floor plan
• Get_utilization
• How to know how many macros are there in the design
• sizeof_collection [all_macros]
• Floorplan Creation
• create_floorplan -left_io2core 20 -bottom_io2core 20 -right_io2core 20 top_io2core 20  \ -core_utilization 0.7 --core_aspect_ratio 1.0
• How to apply the Keepout margin
• set_keepout_margin  -type hard -all_macros -outer {2 2 2 2}
• How to know how many clocks are there in your design
• sizeof_collection [get_clocks]
• How to get the Core area
• get_attribute [get_core_area] bbox
• How to get the Die area
• get_attribute [get_die_area] bbox
• How to find the Area of the cell
• report_area
• How to find the Reference cells area
• report_references
• How to find the Design statistics
• check_physical_design   -design_statistics
• How to know the Hierarchy information
• set_hierarchy_color -cycle_color
• How many Layer are there in the design
• get_layers
• How many Nets are there in the design
• get_nets
• Port information
• get_ports
• How to get the exact cell Location
• get_location cellname
• How to find the cell delay 
• report_delay _calculations -from  xyz/a -to xyz/B
• Libraries information
• get_libs
• Physical library information
• get_physical_libs
• How many buffers are there in the design 
• sizeof_collection [get_bufers]
• How many no of Inputs are there in the design 
• sizeof_collection [get_inputs]
• No of Outputs
• sizeof_collection [get_outputs]
• How to know no of Ports
• sizeof_collection [get_ports *]
• How to know Cell count
• sizeof_collection [get_cells]
• How to know Registers count
• sizeof_collection [get_registers]
• How to know Alternative lib cells of the cells
• get_alternative_lib_cell cell_name
• How to know Path group information
• get_path_groups
• How to know how many site rows are there in the design
• sizeof_collection [get_site_rows]
• How to find the Pins of the cell
• get_pins -of_objects cells_name
• How to know Timing qor of the design
• report_timing
• How to know Hold violations in the design 
• report_timing -delay_type min
• How to know Setup violations in the design 
• report_timing -delay_type max
• How to know all violated paths in the design
• report_constraint -all_violators 
• How to know DRC violations in the design 
• report_constraint -all_violators -max_transistition
• report_constraint -all_violators -capacitance
• How to know Design QOR (Report_qor)
• report_qor
• How to create bound
• create_bound -coordinates {{x1 y1}  {x2 y2}} -type hard/soft/Exclusive -object_list {cell1 cell2 cell3} 
• How to get how many bounds are present in the design
• get_bounds
• How to get the number of blockages in  design
• Get_placement_blockage
• How to create the placement blockage
• create_placement_blockage -coordinates { {x1 y1} {x2 y2}} -type hard/Soft -name blockagename
• create_placement_blockage -coordinates { {x1 y1} {x2 y2}} -type partial -blocked_percentage x -name blockagename.