Tie cell

Tie cells

• Tie cells are the connected to the whose input is constant high/constant low we will connect the tie cell to connect the gate terminal of the transistor to either power or ground 
• In lower technology nodes, tie high and tie low cells are used to avoid the direct gate connection to the power or ground network
• If the gate terminal is connected to power/ground the transistor might be turned on/off due to voltage fluctuations in power/ground net or some time gate may damage due to high power fluctuations. so that is the reason we will connect the tie cells between power and gate terminal of the transistor.
• Tie cells are connected near to the gate terminal
• Tie hi cells are connected to VDD
• Tie lo cells are connected to VSS
• These cells are apart of std_cell library
• In Placement stage tool will place the tie cells based on fanout 

Command :

• SetTieHiLoMode -cell "TIEHI TIELO"  -maxfanout 10
• addTieHiLo -powerDomain Power domain name

After adding the Tie cells we need to apply the global nets
globalNetConnect VDD -type tiehi -pin VDD
globalNetConnect VSS -type tielo -pin VSS
applyGlobalNets