Power Analysis
Inputs For power Analysis
- Netlist
- Constraints
- Upf
- Liblist
- Vcd name
- Tb_top_instance
- Ptpx_clock_period
- Rail Names
- Sdf (Optional)
- Spef (Optional)
- Mapping file
Netlist: -
-We should Provide the flat netlist otherwise should miss the interface information
-We should mention the Netlist of ram's because who libs don't have the Power information
-We should mention the Top-level Netlist and black level Netlists
Liblist:
-Give all the standard cells and memories Libs which will have the power information
Spef
-Spef contains the wire capacitance
Constraints
-From this file, we can read the transition of the Pin (If you have already flat constraints, you can use it otherwise use hierarchical constraints because we are not considering the False path, multi cycle paths, and Half cycle paths
UPF:
-Where you have the Power connectivity and voltage, Rail information
VCD:
-We can get the Activity information from this File
TB_top_instance:
-For which black do you want to do the power analysis this will indicate that hm
PTPx_clk_period:
-We can take the Dominant clock, clock period for ptpx because it will reach the maximum percentage of the flops
Rails:
-Rail names we can get them from the UPF file
