What is the sanity checks you have done for STA?

 Sanity checks for STA:

• Linking Checks:
• We need to check., is there any missing modules or missing pins in a library. this is done by link command.
• Constraint checks:
• In constraint checks we need to check the SDC, i.e. if there are any no-clock, no-input delay, or unconstrained endpoints. this can be done by the check_timing command.
• Parasitic checks:
• In parasitic check we need to check the not annotated nets

How to fix DRV violations

 Max transition violations

• Upsize the cell.
• Insert a buffer when the net is dominant.
• Buffer can be replaced with inverter pair.
• Move the cells nearer.
• Vt swapping from HVT cells to LVT cells
• Metal width increases 
• Metal jogging from lower to higher metals

Max cap/Fanout

• Upsize the cell
• Load splitting.
• Cloning
• Swapping