Uncertainty

Uncertainty:

Uncertainty is nothing but the combination of skew, jitters and PD margins is called as Uncertainty

At Placement stage 

Setup uncertainty:

Take uncertainty with the combination of skew (5 to 10% of clock period) + jitter (1% of clock period) + Pd extra margin (50ps) for setup

Hold Uncertainty:

Take uncertainty with the combination of skew (5 to 10% of clock period) + Pd extra margin (10 to 15ps) for hold jitter won't be there, in hold uncertainty because they hold does not depend up clock period

At Clock Tree Synthesis

Setup uncertainty:

Take uncertainty with the combination of jitter (1% of clock period) + Pd extra margin (50ps) for setup

Hold Uncertainty:

Take uncertainty value-based on Pd extra margin (10 to 15ps) for setup jitter won't be there in hold uncertainty because they hold does not depend up clock period

After propagating the clock skew will be Met so skew is 0

Routing

Remove entire uncertainty value from the SDC


foreach_in_collection  clk [all_clocks] {set_clock_uncertainty -setup 1.3 $clk}
foreach_in_collection  clk [all_clocks] {set_clock_uncertainty -hold 1.2 $clk}
get_property [all_clocks] set_uncertainty
get_property [all_clocks] hold_uncertainty

setAnlaysisMode -check_type setup
get_property [all_clocks] set_uncertainty

setAnlaysisMode -check_type hold
get_property [all_clocks] hold_uncertainty

clock transition and input transition

set_input_transition 0.5 [get_ports port_name]
set_clock_transition 0.5 clk

Duty cycle = Active pulse width / entire clock period
what is the duty cycle of a clock with the period of 10, and the waveform is {2 7}

Duty cycle = {falling edge -rising edge} / clock period

clock jitter:
from cycle to cycle clock period and duty cycle can change slightly due to clock generation circuitry
is called as jitter

skew: the difference in clock arrival time is called skew

Multiple clock domains:
worst-case data transfer:

1. find the LCM of both the clock periods
2. align the clock rising edge of both clocks

set_max_delay -from [all_registers -clock clk1 -clock_pins] -through U10/Y -to [all_registers -clock clk1 -clock_pins] 2 -combinational_from_to

report_timing --from [all_registers -clock clk1 -clock_pins] -through U10/Y -to [all_registers -clock clk1 -clock_pins] -path_type full_clock

Drive adjustment: The difference between the rise delay with load -rise delay with zero load

Script to report of the endpoints and startpoints slack of top 1000 failing paths

set rpt [report_timing -max_paths 1000 -max_slack 0 -collection]
foreach_in_collection r $rpt { puts "Endpoint: [get_property [get_property $r capturing_point] hierarchical_name] \t Startpoint: [get_property [get_property $r launching_point] hierarchical_name] \t Slack: [get_property $r slack]" }

Output:

Synopsis design constrains

Example SDC File:
create_clock  -name SYS_CLK -period 10 -waveform {0 0.5} [get_ports PORT_NAME]
create_generated_clock  -name GEN_SYS_CLK -source PORT_NAME  -divide_by 2 
create_clock -name V_SYS_CLK -period 10 -waveform {0 5}

set_input_delay -max 3 -clock SYS_CLK [get_ports port_name]

set_output_delay -max 7 -clock SYS_CLK [get_ports port_name]

set_max/min_delay -max 3 -clock SYS_CLK [get_pins Pin_name]
set_multicycle_path -setup 3 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_multicycle_path -hold 2 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_driving_cell -lib_cell BUFX2  [get_ports Port_name]
set_load 0.9 [get_ports out[10]]

set_case_analysis 1 [get_ports SE]

set_case_analysis 0 [get_port TM]

set_dont_use [get_lib_cells RAM2P_128x16_ss_1v08_125c_syn/RAM2P_128x16]

set_propagated_clocks [get_clocks*]

set_disable_timing [get_cells cell_name]

set_clock_uncertainty 0.250 -setup [get_clocks CLK]
set_clock_uncertainty 0.100 -hold [get_clocks CLK]
set_max_delay 5.0 [get_ports port_name]
set_load 2 [get_ports port_name]
set_input_transition 1.0 -clock clk [get_ports port_name]

Synthesis

Synthesis

Tools used: Genus/RC compailer
What is Synthesis

• Synthesis is a process of converting RTL code to Gate_level_netlist is called synthesis

Why Synthesis:

• To manufacture the behavioral code ,so we are converting to Gate level netlist

Inputs to Synthesis 

• Libraries
• SDC
• RTL code (synthesizable)
• technology File
• Lef file

Outputs of Synthesis

• Synthesized SDC 
• Synthesized Netlist (.v)

Goals of Synthesis

• To get a gate level Netlist
• Inserting clock gates
• Logic optimization
• Inserting DFT logic
• Logic equivalence between RTL 
• The area will decide (area got reduced by doing the optimization)
• Gate count will decide (based on the logic and optimization process)

create a File with the name of flist we will include the all the Verilog netlists like top module sub-module netlists the below web address do point out the flist file

https://nagarajuphysicaldesign.blogspot.com/2019/11/flist.html

create one sdc file and you can define the clock in that file at clock port like
create_clock -name clk -period 10 -waveform {0 5}  [get_ports clock_port name}
the below path will address the sdc file

https://nagarajuphysicaldesign.blogspot.com/2019/11/synopsis-design-constrains.html

> genus -f scripts

after the synthesis it will provide the synthesized netlist, we will do the sanity checks in Genus for timing as well as design-related checks

1. Check_timing
2. Check_design 

• In flist file keep top-level netlist first and run the synthesis 
• genus provides the unresolved references for sub-modules which are defined in Top-level netlist
• 100% genus will provide the unresolved reference for all submodules which are defined in top module 
• If genus doesn't provide the unresolved references for specific submodule please check the netlist, if is there any ifdef statements are presented or not
• If the top-level netlist has ifdef statement is defined before for that particular submodule genus won't provide the unresolved references for that submodule you can define the ifdef statement name in scripts file by the following command
• read_hdl -f flist -define {"abcd" "efgh"}  
• If you get the unresolved references in the design you can include that module netlist in the flist file and re_run the synthesis until to clear the unresolved references.
• If your design has more flops you can create the block boxes 
• first, check for a two-dimensional array (2D_register) are there  in Verilog netlists, in netlist path, if the register count is more than two hundred  you can create it as a block box
• You can create an empty module for that and include in flist and rerun the synthesis, and it provides the empty module
• this empty module consists of the only module, instance name input-output and inout information it does not has any information 

Process of Synthesis

1. Translation
2. Mapping
3. Optimization

• If your design has constants you can remove by placing the buffers without any optimization

llength [get_db ports -if {.direction==in}]
llength[ [get_db ports -if {.direction==out}]
report_timing -lint .... will give the unconstrained path details

1. Translation:

• Process of converting behavioral code to generic Boolean algebra, It is a technology independent
• For Gtech library we don't have timing inforamtion

2. Mapping

• Selecting the suitable cell from the Technology library it is technology dependent based on input tool will pick the suitable cell from the lib

3. Optimization:

• Optimize the logic ,it will remove the  redundancy logic will be deleted
• Tool will optimize for the area power and performance.

4. Empty module:

• It has only inputs and outputs information, it doesn't have any logic inside the module definition.

5.Unresolved references

• Module definition is present but timing library is missing is called unresolved references 

6.Block_Box

• Macros are block boxes ,there is no functional information but it has timing info 

7.Elaborate:

• Translate the design into its GTECH representation
• Allows changing the parameters values defined in the source code replace the HDL arithmetical operators in the code with the design ware component
• It will check for the sub modules in the Top module ,if there are any gate-level netlists read in with the RTL files, Genus automatically links the cells to their references in the technology library during elaboration.
• It links the design automatically

8).link:  It will link the Design

9). what happens during optimization techniques

• Path adjustment
• Path grouping
• Re-timing
• Tns optimization
• Ungrouping

10). What are the different stages of Optimization in synthesis

• Architectural optimization
• Sharing the sub expressions
• Sharing the resources
• Selecting the design ware components
• After completion of this optimization  design is represented GTECH format
• Logical optimization 
• Will do Boolean algebraic optimization
• Gate level Optimization
• During this stage the logic is converted to logical gate level netlist
• Incremental optimization
• redundancy logic will converted to equivalent gate

11). What is retiming

• Retiming is an advanced optimization technique where registers are re-positioned to reduce cycle time or area without changing the input-output latency of the design. 
• This technique is best fitted for a design that can be pipe lined. 
• The drawback of this technique is, possible problem in formal verification.
• Retiming can be enabled at the top level or selective modules using the ‘retime’ attribute.
• Retiming can recover sequential area from a design with both easy to meet timing goals and a positive slack from the initial synthesis.
• Retiming a design that does not meet timing goals after the initial synthesis could impact total negative slack: the paths with the better slack can be “slowed down” to the range of worst negative slack

12).Path Adjust

• Tightening the constraint on a selective path will make the path become more critical and force Genus to work harder on it. 
• This trick can help closing timing for a small number of violating paths. 
• The following constraint needs to be set before mapping
• path_adjust -delay <> -from -to 

6).Boundary Optimization:

• Propagation of constant across the boundary
• Propagation of equal and opposite information across the hierarchy
• propagation of unconnected Port information across hierarchy
• Pushing of inverters across the hierarchy

13).Ungrouping :

• ungrouping merges the sub design of a given hierarchy into the parent cell or design ,it removers the hierarchical boundaries and allows design compiler to improve the timing by reducing the levels of logic and to improve the area and sharing logic

Few commands :

• check_timing_intent
• checkDesign -all

https://www.blogger.com/blog/post/edit/7948084828664881049/3698505313912971628#

Flist

/root/users/username/design/synthesis/rtl/verilog/submodulename.v
/root/users/username/design/synthesis/rtl/verilog/sub_modulename.v
/root/users/username/design/synthesis/rtl/verilog/design_name_Top.v

Representation of the Parasitic

Parasitic representation

DSPF: Detailed standard parasitics Format
RSPF: Reduced standard parasitics Format
SPEF: Standard parasitic extraction Format

• Standard parasitics Extraction Format interconnect parasitics depend on process. SPEF supports the specification of best-case, typical, and worst-case values. 
• These triplets are allowed for R, L and C values, port slews and loads. By providing a name map consisting of a map of net names and instance names to indices, the SPEF file size is made effectively smaller, and more importantly, all long names appear in only one place.

DSPF: Detailed standard parasitics Format:

• Detailed parasitics are represented in SPICE format, SPICE Comment statements are used to indicate the cell type, pin capacitance
• The resistance and capacitance values are in standard SPICE syntax and the cell instantiations are also included in this representation. 
• Merits:
• DSPF file can be used as an input to a SPICE simulator itself. 
• Drawback
• The DSPF syntax is too detailed and verbose with the result that the total file size for a typical block is very large.

RSPF: Reduced standard parasitics Format

• These parasitics are represented in reduced format and it involves in voltage-controlled current sources.
• Detailed parasitics are reduced and mapped into Reduced format it can be read into SPICE Simulators
• Drawbacks:
• Not represented for bidirectional signal flow

Assign statements

Netlist

If your Netlist has assign statements tool doesn't understand these statements, so you have to remove the assign statements by setting the below command/ replace the constants with buffers /add tie_cells

• set init_remove_assigns 1

The tool will replace the assigns with buffer

1. The default behavior of Verilog writer in innovus is to skip unconnected pins when writing out a Verilog netlist
2. setExportMode -fullPinout true
3. saveNetlist

How to remove assign statements that involve inout ports
The assign statement, in this case, can be removed using the insert_io_buffers utility
command:

• insert_io_buffers -isolate_top outs

• Removes assigns that involve only internal "wires".
  For example, in the code below, assign n2 = n1 is removed.
  module top();
    wire n1, n2;
    assign n2 = n1;
    BUFX2 u1(.Y(n1));
    BUFX2 u2(.A(n2));
    endmodule
  becomes
  module top();
    wire n1;
    BUFX2 u1(.Y(n1));
    BUFX2 u2(.A(n1));
    endmodule
• Removes assigns that involve only one port.
  For example, in the code below,  assign p1 = n1  is removed.
    module hier(p1);
    output p1;
    wire n1;
    assign p1 = n1;
     BUFX2 u1(.Y(n1));
    endmodule
  becomes
    module hier(p1);
    output p1;
     BUFX2 u1(.Y(p1));
    endmodule
  
  
• Rewires nets with feedthrough assigns that involve at least two ports, at some higher level:
  module hier2 (
            i,
            o);
       input i;
       output o;
       assign o = i ;
       BUFX2 u1 (.A(i));
    endmodule
    module hier (
            i,
            o);
       input i;
       output o;
  
  
       hier2 u1 (.i(i),
            .o(o));
    endmodule
    module top ();
       // Internal wires
       wire i;
       wire o;
       BUFX2 u1 (.Y(i));
       hier u2 (.i(i),
            .o(o));
       BUFX2 u3 (.A(o));
    endmodule
  
  
  becomes
  
  
  module hier2 (
            i,
            o);
       input i;
       output o;
  
  
       BUFX2 u1 (.A(i));
    endmodule
    module hier (
            i,
            o);
       input i;
       output o;
       hier2 u1 (.i(i));
    endmodule
    module top ();
       // Internal wires
       wire i;
  
  
       BUFX2 u1 (.Y(i));
       hier u2 (.i(i));
       BUFX2 u3 (.A(i));
    endmodule

Wire Load Models

NLDM: (Non-Linear Delay Model)

These NLDM models have been utilized when the effect of interconnect resistance is small. In the presence of resistive interconnect, the delay calculation methodologies retrofit the NLDM models by obtaining an equivalent effective capacitance at the output of the cell.

CCS Wire load Model
The given input transition time and output load, the output current waveform as a function of time is available.

Macro Placement Guide lines

Macro Placement Guidelines

• Fly-line Analysis (For Connectivity information)
• Macro keep-out (For Uniform Standard Cell Region)
• Channel Calculation (Critical for Congestion and Timing)
• Avoid the odd-shaped area for Standard Cells
• Funnel-shaped Macro Placements are preferred
• Fix the Macro locations, so that tool won't alter during Optimization
• Place macros around the chip periphery, so that core area will be clustered
• Consider connections to fixed cells when placing Macros
• In Advanced Technology Nodes Macro Orientation is fixed since the Poly Orientation can’t vary, so there will be restrictions in Macro Orientation
• Reserve enough room around Macros for IO Routing
• Reduce open fields as much as possible
• Provide necessary Blockages around the Macro

Congestion and It's reduction Techniques

Congestion

Congestion: If the number of routing tracks available for for routing in one particular area is less than the required routing tracks then the area said to be congested.
Congestion : Required Tracks/Available Tracks

10/5 in a 2D congestion map : There are 10 routes that are passing through a particular edge of a Global Route Cell (GRC), but there are only 5 routing tracks available. There is an overflow of 5.

Two major categories: Global Congestion and Local Congestion

Global Congestion: This occurs when there are a lot of chip-level or inter-block wires that need to cross an area.
Local Congestion: This occurs when the floorplan has macros and other routing blockages that are too close together to get enough routes through to connect to the macros

Causes for Routing Congestion:

1. Missing Placement Blockages
2. Inefficient floor plan
3. Improper macro placement and macro channels (Placing macros in the middle of floor plan etc.)
4. Floorplan the macros without giving routing space for interconnection between macros
5. High Cell Density (High local utilization)
6. If your design had more number of AOI/OAI cells you will see this congestion issue
7. Placement of standard cells near macros
8. High pin density on one edge of block
9. Too many buffers added for optimization
10. No proper logic optimization
11. Very Robust Power network
12. High via density due to dense power mesh
13. Crisscross IO pin alignment is also a problem
14. Module splitting

Congestion Reduction Techniques:

1. Add placement Blockages in channels and around macro corners
2. Avoid fly line Crisscrosses
3. Review the macro placement
4. Apply the cell padding (If congestion due to pin density)
5. Apply the Partial blockage (If congestion due to cell density ) 
6. Reduce local cell density using density screens 
7. Reordering scan chain to reduce congestion 
8. Congestion driven placement with high effort 
9. Continue the iterations until good congestion results 
10. Density screen is applied to limit the density of standard cells in an area to reduce congestion due high pin density

Floor Plan Flow

Floor Plan Flow

Floor plan Steps:

1. Aspect Ratio
2. Utilisation
3. IO clearance
4. Channel Spacing
5. Offset Value
6. Macro Placement
7. Channel Spacing 
8. Alignment of Macros
9. Use Proper Blockages
10. IO Pin Assignment
11. Add End caps
12. Add Well Taps

Floor plan Reports

1. checkFPlan -reportUtil
2. checkPlace
3. Check_timing -verbose
4. CheckNetlist
5. CheckUnique
6. Report_qor
7. Report_timing
8. checkPinAssignment
9. checkDesign -all
10. report_constraints
11. all_analysis_views
12. report_analysis_summary

How To fix the Hold time violations

Hold time violations fixing Techniques

The following techniques are used to fix the Hold time violations

1. Down-size the cell
2. LVT to HVT conversion
3. Add Delay cell on Data path

1).Down-size the buffer

• get_cells
• get_lib_cells -of_object cell_name  (which cell you want to down-size NOR4X0_HVT)
• get_alternative_lib_cells cell_name
• size_cell cell_name saed32hvt_ff1p16vn40c/NOR2X0_HVT (corresponding cell name along with Library )

2).LVT to HVT conversion

• get_cells
• get_lib_cells -of_objects U453 (cell name NOR4X0_LVT)
• size_cell U453 NOR4X0_HVT  (U453 instance name of the cell)

3).Add Delay cell on Data path

• insert_buffer net_name DELX4

Note: Here cell name means Instance name

SETUP TIME Violations fixing Techniques

SETUP TIME Violations fixing Techniques

The following techniques are used to fix the Setup time violations

1. Up-size the cell
2. HVT to LVT conversion
3. Add buffer on Data path

1).Up-size the buffer

• get_cells
• get_lib_cells -of_object cell_name  (which cell you want to up-size NOR2X0_HVT)
• get_alternative_lib_cells cell_name
• size_cell cell_name saed32hvt_ff1p16vn40c/NOR4X0_HVT (corresponding cell library with cell name )

2).HVT to LVT conversion

• get_cells
• get_lib_cells -of_objects U453 (cell name NOR4X0_LVT)
• size_cell U453 NOR4X0_LVT  (U453 Instance name)

3).Add buffer

• insert_buffer net_name BUFX4

Note: Here cell name means Instance name

How to convert All LVT Cells to HVT cells wise versa

How to convert All LVT Cells to HVT cells wise versa

proc lvttohvt {lvt cell}   {
          set a [get_flat_cells -filter "ref_name=~*LVT*]
          foreach_in_collection bb $a {
                    set cell [get_attribute $$bb ref_name]
                     regsub "LVT" $cell "HVT" hvtname
                     size_cell $bb $hvtname
                }
   }

Script to find the Next cell and Previous cell

How to find the Next cell
proc name {
set n [get_cells -of_objects [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $name -filter "direction==out"]] -filter "direction==in"]]
}

How to find the Previous cell
proc name {
set n [get_cells -of_objects [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $name -filter "direction==in"]] -filter "direction==out"]]
}

CTS Spec

setCTSMode -routeTopPreferredLayer 5 -routeBottomPreferredLayer 4 -routeShielding VSS -routeNonDefaultRule ndr
setDontUse BUFX2 false
setDontUse INVX1 false
setDontUse BUFX2 false
setDontUse INVX1 false
set_dont_touch [get_lib_cells BUFX2] false
set_dont_touch [get_lib_cells INVX1] false
setDontUse CLKBUF* true
setDontUse CLKINV* true
setDontUse DLY* true
## cts targets##
set_ccopt_property target_max_trans 1 (10% clock period)
set_ccopt_property routing_top_min_fanout 35
set_ccopt_property target_skew 1 (10% of clk)
set_ccopt_property -net_type trunk target_max_trans 0.500
set_ccopt_property -net_type leaf target_max_trans 0.400
set_ccopt_mode -cts_opt_type full
#### latency and uncertainty targets#####
set_clock_latency 4 [get_clocks wb_clk]  (40% of clk)
set_clock_uncertainty 1.3 -setup [get_clocks clk] (including 10% skew+1%jitter+200ps margin)
set_clock_uncertainty 1.2 -hold [get_clocks clk] (including 10% skew+100ps margin)
add_ndr ndr -width {Metal4 0.16 Metal5 0.16} -spacing {Metal4 0.14 Metal5 0.14}
create_route_type -name CTS_2w1s -non_default_rule cts2w1s
set_ccopt_property route_type -net_type trunk CTS_2w1s
set_ccopt_property max_fanout 30

Tie cell

Tie cells

• Tie cells are the connected to the whose input is constant high/constant low we will connect the tie cell to connect the gate terminal of the transistor to either power or ground 
• In lower technology nodes, tie high and tie low cells are used to avoid the direct gate connection to the power or ground network
• If the gate terminal is connected to power/ground the transistor might be turned on/off due to voltage fluctuations in power/ground net or some time gate may damage due to high power fluctuations. so that is the reason we will connect the tie cells between power and gate terminal of the transistor.
• Tie cells are connected near to the gate terminal
• Tie hi cells are connected to VDD
• Tie lo cells are connected to VSS
• These cells are apart of std_cell library
• In Placement stage tool will place the tie cells based on fanout 

Command :

• SetTieHiLoMode -cell "TIEHI TIELO"  -maxfanout 10
• addTieHiLo -powerDomain Power domain name

After adding the Tie cells we need to apply the global nets
globalNetConnect VDD -type tiehi -pin VDD
globalNetConnect VSS -type tielo -pin VSS
applyGlobalNets

End Cap Cells and how to place end cap cells in the design

END CAP CELLS

• End cap cells are pre placed physical only cells it has only physical connectivity 
• End cap cells are placed at the end of each site row [left and right side of the row]
• These library cells don't have signal connectivity
• They connect only to the power and ground rails once power rails are created in the design
• Each end of the core row, left and right, can have only one end cap cell specified
• However, you can specify a list of different end caps for inserting horizontal end cap lines, which terminate the top and bottom boundaries of objects such as macros
• End caps have a fixed attribute and cannot be moved by optimization steps
• A core row can be fragmented (contains gaps), since rows do not intersect objects such as power domains. For this, the tool places end cap cells on both ends of the un-fragmented segment
• while doing the fabrication of the chip the corner cells may get damage it leads to functional failure to resolve this issue will place the end cap cells at the end of the site rows, in this case end cap cells are protecting to the logical cells (Std cells). 

Command:

setEndcapMode -rightEdge FILL1 -leftEdge FILL1

addEndCap -prefix endcap -preCap FILL1 -postCap FILL1 

example: If your design is multi voltage we use the following command to place the end cap cells

• addEndCap -prefix endcap -preCap FILL1 -postCap FILL1 -powerDomain PD1
• addEndCap -prefix endcap -preCap FILL1 -postCap FILL1 -powerDomain PD2

Note: FILL1 cell i consider as a EndCap cell and PD1, PD2 are power domains

Frequently Asking questions on PD

Synthesis

1. What is Synthesis
2. Which tool is using for the synthesis
3. What are the inputs and outputs of Synthesis
4. How to resolve the check_timing_intent issues in Genus
5. How did you resolve the unresolved reference issue in the genus
6. What is  "Flist" , what does it contains
7. What is RTL Code
8. what synthesis guy will do if the netlist is not good?
9. What is the wire load model?
10. what is the NLDM wire load model? When will you use the NLDM Model
11. What is the ccs wire load model? 
12. How do we reduce the Interconnect resistance
13. What is the wire load model?  Explain its classifications
14. How  to represent the  Extracted parasitics
15. what is DSPF? Explain its demerits
16. What is RSPF? Explain its disadvantages
17. What is SPEF

Physical Design

1. What are the inputs for PNR
2. In innovus which file should read first
3. What does SDC contain
4. What does .tf contains
5. While running PNR flow which file should read first?
6. Where do we get the leakage power and voltage information
7. what does netlist contains
8. What is the difference between tracks and Metal layers
9. What is CPF
10. What is Aspect Ratio
11. What is the effect of Aspect Ratio in your design
12. What is utilization
13. How do we calculate the chip utilization
14. What is you're starting utilization
15. How to decide your core Area
16. What is your Row height ?
17. What is the offset value? what is the need for offset value in your design and what is the offset value of your design?
18. What is Channel Spacing
19. How to Calculate the Channel spacing
20. How many types of  Floor plans are there? which type of floor have you done for your design
21. What is a black box
22. Where do we place the macros in your design ? on what bases did you place the macros
23. What does the meaning of Fly lines? how many types of Fly lines are there in your design
24. What is abutted  and non abutted floor plan?
25. What is the meaning of the ORIENTATION
26. What is the pitch of the Highest metal layer in your design
27. Which metal layers are blocked by the macro pins
28. How many pins are there for a one hierarchy macro family 
29. How many hierarchy's are there in your Design
30. What is the impact on your design ? if i place the macros inside the core Area
31. How many Metal Layers are there in your design
32. What is Physical cells
33. Which Physical cells are placed  in floor plan stage?
34. Why we need to use the well taps in your design
35. What is the need of END cap cells
36. What are the inputs for power plan
37. How many stripes are there in your design
38. What is stripe ,follow pin, rail,Ring
39. What is the width of the Ring
40. Which metal layers are prefers for RING and why ?  
41. Which metal layer is used for Ring and why?
42. What is set to set distance in your design
43. Which metal layers are used for stripes why?
44. What are the checks you have done after the power plan?
45. How many opens and shorts are there in your design
46. After the power plan, what is your utilization
47. What is the area of  your design
48. What is power?
49. What is a dangling net? If your design has dangling nets on how to resolve this issue
50. What is Power EM? What is Signal EM
51. What is the impact on Timing by EM violation
52. What is Antenna Effect?
53. What is IR Drop? how many types of IR Drop are there in your design?
54. What is the Impact of IR Drop on timing?
55. What is the impact of the Power EM in your Design
56. What are the disadvantages of the Signal EM
57. What is SRoute?
58. What is LEVEL SHIFTER? where do we use the Isolation cells in your design
59. What is Isolation cells? Which cells are used as Isolation cells
60. What is Retention flops? What is the need for this in your design 
61. What is always on Domain?
62. What is the switch cell?
63. What is the target IR drop in your domain
64. How many power domains are there in your domain
65. What is the placement?
66. What is placement flow?
67. What is SCAN DEF
68. What does Scan def contains
69. What are the checks have you done on after the placement
70. What is Congestion 
71. What are the different Techniques have you used to reduce the Congestion
72. Where did you observe the congestion in your design
73. What is Cell padding
74. After applying the Cell padding what kind of issue will come
75. What is the difference between Module padding and  instance padding
76. After applying the Cell Padding what is the impact on your design
77. Why padding is required?
78. What is pin density?
79. Due to which cells did you get the Pin density
80. What is cell Density
81. What is the density ? after the placement of the design
82. What is Tie cell? 
83. What is the need to tie cell 
84. Where do we place the tie cells and what is the fanout of the Tie cell in your design
85. Which cell is there in the Congestion Hot spot.
86. Which timing checks we will do after the placement
87. Why hold time is not considered at the placement stage
88. What is the difference SCAN FLOP and Normal Flop
89. If I am unable to meet the timing what should I do? at the placement stage?
90. If I insert a buffer in test mode will it impact functional mode? 
91. What you do in Test mode for timing?
92. What you did in test mode for timing closure?
93. What are the violations you see in test mode?
94. How to fix the SETUP violations
95. How to fix the Hold violations
96. How to fix the DRC Violations
97. How to fix the Transition violations
98. How to fix the Max cap violations
99. While fixing the cap violation where do we add the Buffer
100. What is the typical Buffer delay?
101. What is the typical Delay cell delay?
102. What is Scan chain reordering?
103. What is the impact on design after scan chain reordering
104. What is the difference between the Clock buffer and Normal buffer
105. What is Transition in STA point of view
106. Will you route the signal route without CTS? 
107. What does DEF contains
108. What are the inputs and outputs of clock tree synthesis
109. Which cells are used to build the clock tree and why
110. If i use only clock inverters to build the clock tree what is the impact on the design
111. If i use only clock buffers to build the clock tree what is the impact on the design
112. If i use both clock inverters and clock buffers what is the impact on design
113. What is CTS spec
114. What does CTS spec file contains
115. Why Clock tree synthesis is required
116. What are the Objects of clock tree synthesis
117. What is insertion Delay?
118. Which Metal layer is used for clock route
119. In which corner did you build the corner?
120. Why clock uncertainty is specified for a clock?
121. If you design have more skew what is the impact on you are design
122. If insertion delay is more what will happens in your design?
123. What is skew balancing
124. What is use_full skew? where do we add the useful skew in your design
125. What is cross talk? how to control the cross-talk
126. Cross talk fixing techniques?
127. What is cross talk noise? how to reduce the cross talk noise
128. What is cross talk delay 
129. what is the output of the cross-talk tool
130. What is the Min Pulse Width violation? how to resolve these violations
131. Why min pulse width violation will cause? 
132. On which path min pulse width violation will cause? and why?
133. What is the importance of the transition?
134. What are the extracting tools do we have?
135. Define

• skew
• slack
• uncertainty
• jitters
• transition
• slew
• cross-talk
• arrival time
• required time
• latency
• capacitance
• input delay
• output delay
• setup time
• hold time
• recovery time
• removal time
• multi-cycle paths
• false paths
• half cycle paths

SED COMMANDS

SED COMMANDS

Insert a blank line after each line /Insert two blank lines

• sed G filename.txt
• sed 'G;G' filename.txt

Delete the blank lines

• sed '/^$/d' filename.txt

Insert 5 spaces to the left of every lines

• sed 's/^/     /' filename.txt

To delete the particular line

• sed '10d' filename.txt

To delete the lines range from p to q

• sed '5,10d' filename.txt

To delete nth to end line

• sed '10,$d' filename.txt

To delete the matched pattern

• sed '/Nagaraju/d' filename.txt

To delete the lines which matches the pattern and 5 lines after to that pattern

• sed '/Nagaraju/,+5d' filename.txt 

To print the lines range from 10 to 50 of the file

• sed -n '10,50p' filename.txt

To print the lines except that range from 5 to 10

• sed -n '5,10d' filename.txt

To print the particular line and to print the lines from 5 to end of the line

• sed -n '10p' filename.txt
• sed -m '5,$p' filename.txt

To print the line which matches the pattern

• sed -n /Nagaraju/p filename.txt

To prints lines from the nth line of the input ,up to that line matches the pattern ,if the pattern lines doesn't found then it print up to the end of the file

• sed -n '1,/Nagaraju/p' filename.txt

To replace the pattern matches in the entire file with g without g current position of the line

• sed 's/Raju/Nagaraju/g' filename.txt

To replacing the nth occurrence of the pattern

• sed 's/Raju/Nagaraju/2' filename.txt

To replacing pattern on a specific line number 

• sed '10 s/Raju/Nagaraju/' filename.txt

To replacing the pattern on a defined range and ignoring the case

• sed '10,20 s/Raju/Nagaraju/i' filename.txt

Replace one pattern followed by the another pattern

• sed '/is/ s/Raju/Nagaraju/' filename.txt

Replace a pattern with other except in the nth line

• sed -i '5!s/Raju/Nagaraju/' filename.txt

How to displace the alternative line

• sed -n '1~2p' filename.txt

How to print pattern1 to pattern 2

• sed -n '/pattern1/,//pattern2/p' filename.txt 

Tar the file
tar -cvf filename.tar filename
Untar the file
tar -xvf filename.tar

GREP COMMANDS

GREP COMMANDS

To search the pattern in a particular file

• grep "Nagaraju" filename.txt

To search a pattern without case insensitive

• grep -wi "nagaraju" filename.txt

To search a pattern before and after the 10  lines

• grep -win -A/B/C 10 "Nagaraju"   filename.txt

To display all file names which contains the searched pattern

• grep -win "Nagaraju"  ./* 

To display other than that the searched pattern

• grep   -v "Nagaraju" filename.txt
• grep   -vE  "pattern1|pattern2" filename.txt

Displaying the count of the number of matches

• grep  -c "Nagaraju"  filename.txt  

To check for the whole words in a file

• grep -w "Nagaraju" filename.txt

To show the line numbers of the matched pattern

• grep -n "Nagaraju" filename.txt

To Display the matched pattern

• grep -o "Nagaraju"  filename.txt

To display the matching pattern that starts/ends with a string

• grep "^Nagaraju" filename.txt
• grep "Nagaraju$" filename.txt

How to grep multiple 

• grep -E "Naga|Raju" filename.txt

GVIM EDITOR

GVIM EDITOR

In Gvim Editor we have three modes 

• Command mode
• Insert mode
• Visual mode

i                            Insert mode
ESC                     Command mode
yy                         Copy
10yy                     To copy 10 lines
p                           Paste
dd                         Delete
10dd                     To delete 10 lines
u                            Undo
J                             Joint back the line
gf                           to the file
:bd                          Back to the file
:vsp                       Vertical split
:sp                         Horizontal split
ctrl+ww                To go the next file
ctrl+a                   Increasing the number 

ctrl+x                   Decreasing the number

:wq!                      Save and close
a                            Insert mode after the  cursor
shift+a                  Insert mode at the end of line
/pattern                Search the pattern
:$                           Cursor will to the last line
:~                           Converting from lower case to upper case
:R                          Replace the file name
:csh                       Entering into Linux shell
gg                          To go to the top of the file
shift+gg                To go to end of the file
100 gg                   To got to 100 line
:set nu                   To set/ Enable the line numbers to view
:set nonu                 To Hide the line numbers /disable the line no view
?                             Back search
^                              It indicate the begging of the line
$                              It indicates the ending of the line
:n                             To move the nth line from current line
h                            To back side of the current cursor position
l                              To go to right of the current cursor position
j                             To go to Down line  of the current cursor position line
k                             To go to the up side of the current position line
:123,321s/old name/new name       To change the old name by new name from starting number(123) to ending number (321)

Ctrl +v    visual mode

Shift+i  and select the number of lines to insert the pattern  at the begging of the lines
write the pattern 
ESC
:s/old name/new name/gc          To change the pattern in the current cursor Position
:%S/old name/new name/g    It will change the every occurrence of the old name by new name    
:%S/$/old pattern/new pattern/gc To replace the new pattern at the end of the lines in a file
:%S/^/raju/gc                               Add raju in beginning of all the lines
:g//d    This will delete the lines wich contains previous searched pattern
:g!//d   This will deletes the other lines which doesn't contains previous pattern
:g/^$/d to delete the empty lines

:%s///n  -->if you search for a pattern in a file  that pattern will highlight, how many times that pattern was there that info it will give (count number)  
:%s/\  /\r/g  it will show one by one line

ctrl+v GJJ to combined all lines to single

%s/\n/pattern\r/g : to print the pattern at the end of the line

:n to examine the file , quickly open and close

:tabnew filename

:%S/\n/pattern\r/g to print the pattern at the end of the every line

:12 , 40 w filename.txt saved it in the file from 12 to 40 lines

:e to update the log file

:args to know the name of the file which we are opened 

:1s/\//\\\//gc   --> to replace the / with \/

:2s/_pattern_/\//gc 

:54 r filename.txt from line number 54 it will replace current file content with the filename.txt data

:g:pattern:d  if the pattern is matched on a line it will delete

:e# , (ctrl+6 or bd) back to directory

:ls ${cwd}/*  it will give the path 

readlink -f file name it will give the abspath