Assign statements

Netlist

If your Netlist has assign statements tool doesn't understand these statements, so you have to remove the assign statements by setting the below command/ replace the constants with buffers /add tie_cells

• set init_remove_assigns 1

The tool will replace the assigns with buffer

1. The default behavior of Verilog writer in innovus is to skip unconnected pins when writing out a Verilog netlist
2. setExportMode -fullPinout true
3. saveNetlist

How to remove assign statements that involve inout ports
The assign statement, in this case, can be removed using the insert_io_buffers utility
command:

• insert_io_buffers -isolate_top outs

• Removes assigns that involve only internal "wires".
  For example, in the code below, assign n2 = n1 is removed.
  module top();
    wire n1, n2;
    assign n2 = n1;
    BUFX2 u1(.Y(n1));
    BUFX2 u2(.A(n2));
    endmodule
  becomes
  module top();
    wire n1;
    BUFX2 u1(.Y(n1));
    BUFX2 u2(.A(n1));
    endmodule
• Removes assigns that involve only one port.
  For example, in the code below,  assign p1 = n1  is removed.
    module hier(p1);
    output p1;
    wire n1;
    assign p1 = n1;
     BUFX2 u1(.Y(n1));
    endmodule
  becomes
    module hier(p1);
    output p1;
     BUFX2 u1(.Y(p1));
    endmodule
  
  
• Rewires nets with feedthrough assigns that involve at least two ports, at some higher level:
  module hier2 (
            i,
            o);
       input i;
       output o;
       assign o = i ;
       BUFX2 u1 (.A(i));
    endmodule
    module hier (
            i,
            o);
       input i;
       output o;
  
  
       hier2 u1 (.i(i),
            .o(o));
    endmodule
    module top ();
       // Internal wires
       wire i;
       wire o;
       BUFX2 u1 (.Y(i));
       hier u2 (.i(i),
            .o(o));
       BUFX2 u3 (.A(o));
    endmodule
  
  
  becomes
  
  
  module hier2 (
            i,
            o);
       input i;
       output o;
  
  
       BUFX2 u1 (.A(i));
    endmodule
    module hier (
            i,
            o);
       input i;
       output o;
       hier2 u1 (.i(i));
    endmodule
    module top ();
       // Internal wires
       wire i;
  
  
       BUFX2 u1 (.Y(i));
       hier u2 (.i(i));
       BUFX2 u3 (.A(i));
    endmodule