Uncertainty

Uncertainty:

Uncertainty is nothing but the combination of skew, jitters and PD margins is called as Uncertainty

At Placement stage 

Setup uncertainty:

Take uncertainty with the combination of skew (5 to 10% of clock period) + jitter (1% of clock period) + Pd extra margin (50ps) for setup

Hold Uncertainty:

Take uncertainty with the combination of skew (5 to 10% of clock period) + Pd extra margin (10 to 15ps) for hold jitter won't be there, in hold uncertainty because they hold does not depend up clock period

At Clock Tree Synthesis

Setup uncertainty:

Take uncertainty with the combination of jitter (1% of clock period) + Pd extra margin (50ps) for setup

Hold Uncertainty:

Take uncertainty value-based on Pd extra margin (10 to 15ps) for setup jitter won't be there in hold uncertainty because they hold does not depend up clock period

After propagating the clock skew will be Met so skew is 0

Routing

Remove entire uncertainty value from the SDC


foreach_in_collection  clk [all_clocks] {set_clock_uncertainty -setup 1.3 $clk}
foreach_in_collection  clk [all_clocks] {set_clock_uncertainty -hold 1.2 $clk}
get_property [all_clocks] set_uncertainty
get_property [all_clocks] hold_uncertainty

setAnlaysisMode -check_type setup
get_property [all_clocks] set_uncertainty

setAnlaysisMode -check_type hold
get_property [all_clocks] hold_uncertainty

clock transition and input transition

set_input_transition 0.5 [get_ports port_name]
set_clock_transition 0.5 clk

Duty cycle = Active pulse width / entire clock period
what is the duty cycle of a clock with the period of 10, and the waveform is {2 7}

Duty cycle = {falling edge -rising edge} / clock period

clock jitter:
from cycle to cycle clock period and duty cycle can change slightly due to clock generation circuitry
is called as jitter

skew: the difference in clock arrival time is called skew

Multiple clock domains:
worst-case data transfer:

1. find the LCM of both the clock periods
2. align the clock rising edge of both clocks

set_max_delay -from [all_registers -clock clk1 -clock_pins] -through U10/Y -to [all_registers -clock clk1 -clock_pins] 2 -combinational_from_to

report_timing --from [all_registers -clock clk1 -clock_pins] -through U10/Y -to [all_registers -clock clk1 -clock_pins] -path_type full_clock

Drive adjustment: The difference between the rise delay with load -rise delay with zero load

Script to report of the endpoints and startpoints slack of top 1000 failing paths

set rpt [report_timing -max_paths 1000 -max_slack 0 -collection]
foreach_in_collection r $rpt { puts "Endpoint: [get_property [get_property $r capturing_point] hierarchical_name] \t Startpoint: [get_property [get_property $r launching_point] hierarchical_name] \t Slack: [get_property $r slack]" }

Output: