Synopsis design constrains

Example SDC File:
create_clock  -name SYS_CLK -period 10 -waveform {0 0.5} [get_ports PORT_NAME]
create_generated_clock  -name GEN_SYS_CLK -source PORT_NAME  -divide_by 2 
create_clock -name V_SYS_CLK -period 10 -waveform {0 5}

set_input_delay -max 3 -clock SYS_CLK [get_ports port_name]

set_output_delay -max 7 -clock SYS_CLK [get_ports port_name]

set_max/min_delay -max 3 -clock SYS_CLK [get_pins Pin_name]
set_multicycle_path -setup 3 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_multicycle_path -hold 2 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_driving_cell -lib_cell BUFX2  [get_ports Port_name]
set_load 0.9 [get_ports out[10]]

set_case_analysis 1 [get_ports SE]

set_case_analysis 0 [get_port TM]

set_dont_use [get_lib_cells RAM2P_128x16_ss_1v08_125c_syn/RAM2P_128x16]

set_propagated_clocks [get_clocks*]

set_disable_timing [get_cells cell_name]

set_clock_uncertainty 0.250 -setup [get_clocks CLK]
set_clock_uncertainty 0.100 -hold [get_clocks CLK]
set_max_delay 5.0 [get_ports port_name]
set_load 2 [get_ports port_name]
set_input_transition 1.0 -clock clk [get_ports port_name]