How to convert Nand gate to Inverter

 NAND Gate:

If both the inputs A and B are same output Y becomes 0 otherwise 1

Truth table of NAND Gate

A     B    Y

0      0     1

0      1     1

1      0     1

1      1     0

Inverter gate 

The output of the gate is reciprocal to the input of the gate is called inversion 

Example:

If you provide the input as 1 the output gone be 0
if you provide the input as 0 the output becomes 1

If  you connect the both inputs  A and B , the output becomes inversion of the input, Mentioned both the inputs A and B which are shorted. so it acts a single input to the NAND gate and it will give the inversion of the input

A   B  Y

0    0   1

1    1   0

How to covert XOR gate to Buffer

 XOR gate:

When both the inputs are different the output becomes one (1), otherwise output becomes zero 

Buffer:

Buffer is used for increasing the signal strength which means it acts as a repeater -the output is same as input

If we connect anyone of the input of the XOR gate is connected to the ground , remaining input what ever the input we given to that gate will get the same output.


Consider input B pin is connected to the ground means 0 , if we provide input to the A pin  XOR gate output pin Y we should get the same (Y=A)


A   B   Y

0    0     0

1    0     1

Power Analysis Inputs

Power Analysis

 Inputs For power Analysis

1. Netlist
2. Constraints
3. Upf
4. Liblist
5. Vcd name
6. Tb_top_instance
7. Ptpx_clock_period
8. Rail Names 
9. Sdf (Optional)
10. Spef (Optional)
11. Mapping file

Netlist: - 

-We should Provide the flat netlist otherwise should miss the interface information

-We should mention the Netlist of ram's because who libs don't have the Power information

-We should mention the Top-level Netlist and black level Netlists

Liblist:

-Give all the standard cells and memories Libs which will have the power information

Spef

-Spef contains the wire capacitance

Constraints

-From this file, we can read the transition of the Pin (If you have already flat constraints, you can use it otherwise use hierarchical constraints because we are not considering the False path, multi cycle paths, and Half cycle paths

UPF:

-Where you have the Power connectivity and voltage, Rail information

VCD:

-We can get the Activity information from this File

TB_top_instance:

-For which black do you want to do the power analysis this will indicate that hm

PTPx_clk_period:

-We can take the Dominant clock, clock period for ptpx because it will reach the maximum percentage of the flops

Rails:

-Rail names we can get them from the UPF file

SDF

-Where we have the exact interconnect and Call delays are present