Congestion and It's reduction Techniques

Congestion

Congestion: If the number of routing tracks available for for routing in one particular area is less than the required routing tracks then the area said to be congested.
Congestion : Required Tracks/Available Tracks

10/5 in a 2D congestion map : There are 10 routes that are passing through a particular edge of a Global Route Cell (GRC), but there are only 5 routing tracks available. There is an overflow of 5.

Two major categories: Global Congestion and Local Congestion

Global Congestion: This occurs when there are a lot of chip-level or inter-block wires that need to cross an area.
Local Congestion: This occurs when the floorplan has macros and other routing blockages that are too close together to get enough routes through to connect to the macros

Causes for Routing Congestion:

1. Missing Placement Blockages
2. Inefficient floor plan
3. Improper macro placement and macro channels (Placing macros in the middle of floor plan etc.)
4. Floorplan the macros without giving routing space for interconnection between macros
5. High Cell Density (High local utilization)
6. If your design had more number of AOI/OAI cells you will see this congestion issue
7. Placement of standard cells near macros
8. High pin density on one edge of block
9. Too many buffers added for optimization
10. No proper logic optimization
11. Very Robust Power network
12. High via density due to dense power mesh
13. Crisscross IO pin alignment is also a problem
14. Module splitting

Congestion Reduction Techniques:

1. Add placement Blockages in channels and around macro corners
2. Avoid fly line Crisscrosses
3. Review the macro placement
4. Apply the cell padding (If congestion due to pin density)
5. Apply the Partial blockage (If congestion due to cell density ) 
6. Reduce local cell density using density screens 
7. Reordering scan chain to reduce congestion 
8. Congestion driven placement with high effort 
9. Continue the iterations until good congestion results 
10. Density screen is applied to limit the density of standard cells in an area to reduce congestion due high pin density