Frequently Asking questions on PD

Synthesis

1. What is Synthesis
2. Which tool is using for the synthesis
3. What are the inputs and outputs of Synthesis
4. How to resolve the check_timing_intent issues in Genus
5. How did you resolve the unresolved reference issue in the genus
6. What is  "Flist" , what does it contains
7. What is RTL Code
8. what synthesis guy will do if the netlist is not good?
9. What is the wire load model?
10. what is the NLDM wire load model? When will you use the NLDM Model
11. What is the ccs wire load model? 
12. How do we reduce the Interconnect resistance
13. What is the wire load model?  Explain its classifications
14. How  to represent the  Extracted parasitics
15. what is DSPF? Explain its demerits
16. What is RSPF? Explain its disadvantages
17. What is SPEF

Physical Design

1. What are the inputs for PNR
2. In innovus which file should read first
3. What does SDC contain
4. What does .tf contains
5. While running PNR flow which file should read first?
6. Where do we get the leakage power and voltage information
7. what does netlist contains
8. What is the difference between tracks and Metal layers
9. What is CPF
10. What is Aspect Ratio
11. What is the effect of Aspect Ratio in your design
12. What is utilization
13. How do we calculate the chip utilization
14. What is you're starting utilization
15. How to decide your core Area
16. What is your Row height ?
17. What is the offset value? what is the need for offset value in your design and what is the offset value of your design?
18. What is Channel Spacing
19. How to Calculate the Channel spacing
20. How many types of  Floor plans are there? which type of floor have you done for your design
21. What is a black box
22. Where do we place the macros in your design ? on what bases did you place the macros
23. What does the meaning of Fly lines? how many types of Fly lines are there in your design
24. What is abutted  and non abutted floor plan?
25. What is the meaning of the ORIENTATION
26. What is the pitch of the Highest metal layer in your design
27. Which metal layers are blocked by the macro pins
28. How many pins are there for a one hierarchy macro family 
29. How many hierarchy's are there in your Design
30. What is the impact on your design ? if i place the macros inside the core Area
31. How many Metal Layers are there in your design
32. What is Physical cells
33. Which Physical cells are placed  in floor plan stage?
34. Why we need to use the well taps in your design
35. What is the need of END cap cells
36. What are the inputs for power plan
37. How many stripes are there in your design
38. What is stripe ,follow pin, rail,Ring
39. What is the width of the Ring
40. Which metal layers are prefers for RING and why ?  
41. Which metal layer is used for Ring and why?
42. What is set to set distance in your design
43. Which metal layers are used for stripes why?
44. What are the checks you have done after the power plan?
45. How many opens and shorts are there in your design
46. After the power plan, what is your utilization
47. What is the area of  your design
48. What is power?
49. What is a dangling net? If your design has dangling nets on how to resolve this issue
50. What is Power EM? What is Signal EM
51. What is the impact on Timing by EM violation
52. What is Antenna Effect?
53. What is IR Drop? how many types of IR Drop are there in your design?
54. What is the Impact of IR Drop on timing?
55. What is the impact of the Power EM in your Design
56. What are the disadvantages of the Signal EM
57. What is SRoute?
58. What is LEVEL SHIFTER? where do we use the Isolation cells in your design
59. What is Isolation cells? Which cells are used as Isolation cells
60. What is Retention flops? What is the need for this in your design 
61. What is always on Domain?
62. What is the switch cell?
63. What is the target IR drop in your domain
64. How many power domains are there in your domain
65. What is the placement?
66. What is placement flow?
67. What is SCAN DEF
68. What does Scan def contains
69. What are the checks have you done on after the placement
70. What is Congestion 
71. What are the different Techniques have you used to reduce the Congestion
72. Where did you observe the congestion in your design
73. What is Cell padding
74. After applying the Cell padding what kind of issue will come
75. What is the difference between Module padding and  instance padding
76. After applying the Cell Padding what is the impact on your design
77. Why padding is required?
78. What is pin density?
79. Due to which cells did you get the Pin density
80. What is cell Density
81. What is the density ? after the placement of the design
82. What is Tie cell? 
83. What is the need to tie cell 
84. Where do we place the tie cells and what is the fanout of the Tie cell in your design
85. Which cell is there in the Congestion Hot spot.
86. Which timing checks we will do after the placement
87. Why hold time is not considered at the placement stage
88. What is the difference SCAN FLOP and Normal Flop
89. If I am unable to meet the timing what should I do? at the placement stage?
90. If I insert a buffer in test mode will it impact functional mode? 
91. What you do in Test mode for timing?
92. What you did in test mode for timing closure?
93. What are the violations you see in test mode?
94. How to fix the SETUP violations
95. How to fix the Hold violations
96. How to fix the DRC Violations
97. How to fix the Transition violations
98. How to fix the Max cap violations
99. While fixing the cap violation where do we add the Buffer
100. What is the typical Buffer delay?
101. What is the typical Delay cell delay?
102. What is Scan chain reordering?
103. What is the impact on design after scan chain reordering
104. What is the difference between the Clock buffer and Normal buffer
105. What is Transition in STA point of view
106. Will you route the signal route without CTS? 
107. What does DEF contains
108. What are the inputs and outputs of clock tree synthesis
109. Which cells are used to build the clock tree and why
110. If i use only clock inverters to build the clock tree what is the impact on the design
111. If i use only clock buffers to build the clock tree what is the impact on the design
112. If i use both clock inverters and clock buffers what is the impact on design
113. What is CTS spec
114. What does CTS spec file contains
115. Why Clock tree synthesis is required
116. What are the Objects of clock tree synthesis
117. What is insertion Delay?
118. Which Metal layer is used for clock route
119. In which corner did you build the corner?
120. Why clock uncertainty is specified for a clock?
121. If you design have more skew what is the impact on you are design
122. If insertion delay is more what will happens in your design?
123. What is skew balancing
124. What is use_full skew? where do we add the useful skew in your design
125. What is cross talk? how to control the cross-talk
126. Cross talk fixing techniques?
127. What is cross talk noise? how to reduce the cross talk noise
128. What is cross talk delay 
129. what is the output of the cross-talk tool
130. What is the Min Pulse Width violation? how to resolve these violations
131. Why min pulse width violation will cause? 
132. On which path min pulse width violation will cause? and why?
133. What is the importance of the transition?
134. What are the extracting tools do we have?
135. Define

• skew
• slack
• uncertainty
• jitters
• transition
• slew
• cross-talk
• arrival time
• required time
• latency
• capacitance
• input delay
• output delay
• setup time
• hold time
• recovery time
• removal time
• multi-cycle paths
• false paths
• half cycle paths