PnR Inputs

Physical Design Inputs

1. Netlist (.V)
2. Synopsys design constraints (.SDC)
3. Libraries (.libs)
4. LEF (Library Exchange Format .lef)
5. Technology File (.tf)
6. TLU+ file

Netlist (.V) 
Synthesis team will provide .V file

It is the combination of the sequential and combinational cells and its connectivity

it contains 

• Module
• Module Information
• Cell & Instance name
• Drive strength
• Inputs
• Outputs
• Wire Information
• Hierarchy Information
• Sub-Module Names 
• Cell Library Information

Synopsys design constraints (.SDC) 
Synthesis team will provide .SDC file

• Clock Definitions
• Clock Names
• Generated Clock Names
• Operating Conditions
• Input and Output delays
• Max and Min delays
• Max_transition
• Multicycle paths
• False paths
• Set_driving_cells
• Set_drive
• Set_load
• Set_disable_timing
• Case Analysis
• Clock_uncertainty

Example SDC File:
create_clock  -name SYS_CLK -period 10 -waveform {0 0.5} [get_ports PORT_NAME]
create_generated_clock  -name GEN_SYS_CLK -source PORT_NAME  -divide_by 2 
create_clock -name V_SYS_CLK -period 10 -waveform {0 5}

set_input_delay -max 3 -clock SYS_CLK [get_ports port_name]

set_output_delay -max 7 -clock SYS_CLK [get_ports port_name]

set_max/min_delay -max 3 -clock SYS_CLK [get_pins Pin_name]
set_multicycle_path -setup 3 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_multicycle_path -hold 2 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_driving_cell -lib_cell BUFX2  [get_ports Port_name]
set_load 0.9 [get_ports out[10]]

set_case_analysis 1 [get_ports SE]

set_case_analysis 0 [get_port TM]

set_dont_use [get_lib_cells RAM2P_128x16_ss_1v08_125c_syn/RAM2P_128x16]

set_propagated_clocks [get_clocks*]

set_disable_timing [get_cells cell_name]

set_clock_uncertainty 0.250 -setup [get_clocks CLK]
set_clock_uncertainty 0.100 -hold [get_clocks CLK]
set_max_delay 5.0 [get_ports port_name]
set_load 2 [get_ports port_name]
set_input_transition 1.0 -clock clk [get_ports port_name]

Libraries (.libs):
Vendor will provide Libraries

Cell Delay = based on input transition and output load

• Setup time
• Hold time
• Removal time
• Recovery time
• Leakage Power
• Dynamic Power
• Delay
• PVT conditions
• Wire load models
• Std.lib
• Macro.lib
• IO lib
• Arcs

LEF (Library Exchange Format(.lef)):

• Std.cell LEF
• Macro LEF
• IO Lef

LEF Contains

• Cell
• Cell name
• Shape
• Size
• Orientation
• Class
• Pin Name
• Port Name
• Layout Geometries
• Blockage
• Antenna Diff Area

Technology File (.tf)

Fab Team will provide the Technology File
Technology file (.tf) in Synopsys Format
Tech_lef in Cadence Format
Technology file contains

• Units
• Mask Name
• Max current density
• Metals 
• Layers
• Vias
• Min width
• Min space
• Pitch
• Lines
• Patterns
• Intensity
• Metal Density
• Antenna Rules
• Width 
• Height
• blink

TLU + File
TLU + File  in Synopsys Format
CapTables in Cadence Format 

• Normal Captable File in 2D format
• Expanded Captable File in 3D format

Tlu+ file contains the RC coefficients 

1. TLU+ Maximum File
• It has Maximum RC values
2. TLU+ Minimum File
• It has Minimum RC values
3. Mapped File
• Mapped file maps the technology file and .itf file for Deriving the RC values

ITF (Interconnect Technology File):

• It describes the thickness and the physical attributes of conductor and dielectric used to extract the RC values for the chip