- saveDesign Dbname.enc
- defOut -floorPlan -scanChain -netlist -routing dbName.def
- saveNetlist dbName.v
- extractRC
- rcOut -spef spef.name -corner <corner_Name>
- streamOut design_name.gds -library lib_name -map stramOut.map
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What is the sanity checks you have done for STA?
Sanity checks for STA: Linking Checks: We need to check., is there any missing modules or missing pins in a library. this is done by link c...
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Sanity checks for STA: Linking Checks: We need to check., is there any missing modules or missing pins in a library. this is done by link c...
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Congestion Congestion : If the number of routing tracks available for for routing in one particular area is less than the required ro...
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VOLTUS Inputs for VOLTUS (power analysis): Technology lefs Tech lef Macro lef Decap lef Buf lef Libraries Verilog netlist DEF (data excha...
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