Timing Constraints

 Input Delay constraints

60%,40% of the clock is input delay

Example:

If your clock time period is 1ns the input delay we should consider 60% of the clock so put 600ps for input delay , which the time taking the signal from the external clock definition point to the input port of your block, remaining 40% will be consider for internal logic of your block.

Output Delay constraints

30%,70% of the clock is output delay

Example

If your clock time period is 1ns ,the output delay we should consider 70 % of the clock so, you put 700ps for output delay which means , time taken by the signal reaching from output port of the block to the external flop D pin, remaining 30% of time we should consider for your block.

Load:-

The load we should consider 0.02femptofarads 

Assume By default 2 to 3 times of the NAND gate input cap 

Driving_cell:-

The thumb rule is 10% of the clock period , If it is more pessimism take 5% of the clock period

NAND gate are will decide the core area

Because the total gate count is equals to the ratio of the total cell area to NAND gate equivalent area