Placements checks

• Congestion
• If the congestion is there in your design first check in which region you got the congestion hotspot
• If it is with cell density use partial blockage , how much percentage you gave to clear the congestion hotspot 
• If it is due to pin density , Use cell padding /keep_out_margin ,how much padding number you gave and for which cell/instance/module
• If congestion is there at Macro pins , think about how to resolve the issue 
• First check is there any sufficient Blockage or not if it is not there give proper blockage
• keep out margin will also helps 
• You may see the shorts on macro pins with routing blockage on it ,so you should reduce the route blockage area on macro 
• Check the channel spacing is there or not otherwise you may see the congestion
• Remember in which metal layer, you got the congestion 
• Timing
• You should take care about the setup time violations not for Hold time violations but it should be under control
• why we did not check the hold time violations at this stage means clock is not yet build, the delay or not real these delays are estimated delays
• If you get the setup time violations check about the flop location, if it is too far use bounds
• Even though setup time is not fixed ,Get the all nets which are there in that path and  you can route it in top metal layer by using specify_net_weight
• Use net guides also you fix the setup time violations set_net_priority which metal layers are used to route first
• If the combinational delay  is more than the clock period you should inform to RTL Team, based on there guidelines use multi_cycle paths
• what is the uncertainty, how much value is there for setup and hold uncertainty 
• What is latency,how much value you gave for both source and network latency
• If data to data to data check is required for a particular module or module ports 
• Density
• check Placement Density
• If the pin density is more ,you have to check the don't touch or don't use attribute on the cells ,If these attributes are not specified tool may use those cells