- Contains Die/core area
- Placed Macro information
- Blockage information
- Placed I/O Pin/pad information
- std cell placement area
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What is the sanity checks you have done for STA?
Sanity checks for STA: Linking Checks: We need to check., is there any missing modules or missing pins in a library. this is done by link c...
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Sanity checks for STA: Linking Checks: We need to check., is there any missing modules or missing pins in a library. this is done by link c...
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Floor plan Reports checkFPlan -reportUtil checkPlace Check_timing -verbose CheckNetlist CheckUnique Report_qor Report_timing checkPinAssig...
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VOLTUS Inputs for VOLTUS (power analysis): Technology lefs Tech lef Macro lef Decap lef Buf lef Libraries Verilog netlist DEF (data excha...
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