Multi cycle paths

• Multi Cycle path is nothing but the data can take more than one clock cycle to capture the data is called as multi cycle path.
• Multi cycle path is a one of the timing Exception
• This timing exception is created between the inter clock domains  
• The domain relationship between the clocks used in multi cycle path

how to set the multi cycle path:

• case 1
• To set the multi cycle path between the flops
• set_multicycle_path -from flop1 -to flop2
• case 2
• Between the clock domains
• set_multicycle_path -from clock1 -to clock2
• case 3

• How to set the multi cycle path for setup and hold
• set_multicycle_path  5 -setup -from [get_clocks clock1] -to [get_clocks clock2]
• set_multicycle_path  4 -hold -from [get_clocks clock1] -to [get_clocks clock2]
• case 4 
• If clock 1 is faster than the clock2
• set_multicycle_path  5 -setup -from [get_clocks clock1] -to [get_clocks clock2] -start
• set_multicycle_path  4 -hold -from [get_clocks clock1] -to [get_clocks clock2] -start
• case 5
• if clock 1 is slower than the clock2
• set_multicycle_path  5 -setup -from [get_clocks clock1] -to [get_clocks clock2] -end
• set_multicycle_path  4 -hold -from [get_clocks clock1] -to [get_clocks clock2] -end

• Note:
• Multi cycle path number is based on the requirement
• if you do multi cycle for setup analysis Nth edge ,you have to do hold analysis at N-1 edge
• based on the fast clock we should put the start and end switch
• if the faster clock is at launching side you should keep start otherwise put end switch

• Benefits of the multi cycle path

• Multi cycle path will improve the timing