Gate level Netlist (.V)

Gate level Netlist (.V)

Synthesis team will provide the Gate level Netlist (.V) file

It is the combination of the sequential and combinational cells and its connectivity

it contains 

• Module

• Module Information

• Cell & Instance name

• Drive strength

• Inputs

• Outputs

• Wire Information

• Hierarchy Information

• Sub-Module Names

Example :

Module andGate (a b c);

input a , b;

output c;

and2x1 g1 (c,a,b) ;

endmodule