- get_clocks
- get_property [get_clocks clock_name] period
- get_property [get_clocks clock_name] uncertainty
- get_property [get_clocks clock_name] latency
- sizeof_collections [get_clocks]
- report_clock_tree
- report_clock_tree -exceptions
- report_clock_tree -level_info
- report_clock_tree -summary
- report_clock_tree -type latency
- report_clock_tree -local_skew
- get_utilization
- get_buffers *CLK*
- set_dont_touch [get_lib_cells */*DLY*] false
- set_dont_touch [get_lib_cells */*CLKBUF*] false
- set_dont_touch [get_lib_cells */*CLKINV*] false
- report_clock_tree_power
- report_clock_tree -interclock_timing
- report_clock_timing -type latency
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Sunday, May 16, 2021
ICC commands frequently used at CTS stage
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What is the sanity checks you have done for STA?
Sanity checks for STA: Linking Checks: We need to check., is there any missing modules or missing pins in a library. this is done by link c...
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Sanity checks for STA: Linking Checks: We need to check., is there any missing modules or missing pins in a library. this is done by link c...
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Max transition violations Upsize the cell. Insert a buffer when the net is dominant. Buffer can be replaced with inverter pair. Move the ce...
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Floor plan Reports checkFPlan -reportUtil checkPlace Check_timing -verbose CheckNetlist CheckUnique Report_qor Report_timing checkPinAssig...
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