Uncertainty

Uncertainty:

Uncertainty is nothing but the combination of skew, jitters and PD margins is called as Uncertainty

At Placement stage 

Setup uncertainty:

Take uncertainty with the combination of skew (5 to 10% of clock period) + jitter (1% of clock period) + Pd extra margin (50ps) for setup

Hold Uncertainty:

Take uncertainty with the combination of skew (5 to 10% of clock period) + Pd extra margin (10 to 15ps) for hold jitter won't be there, in hold uncertainty because they hold does not depend up clock period

At Clock Tree Synthesis

Setup uncertainty:

Take uncertainty with the combination of jitter (1% of clock period) + Pd extra margin (50ps) for setup

Hold Uncertainty:

Take uncertainty value-based on Pd extra margin (10 to 15ps) for setup jitter won't be there in hold uncertainty because they hold does not depend up clock period

After propagating the clock skew will be Met so skew is 0

Routing

Remove entire uncertainty value from the SDC


foreach_in_collection  clk [all_clocks] {set_clock_uncertainty -setup 1.3 $clk}
foreach_in_collection  clk [all_clocks] {set_clock_uncertainty -hold 1.2 $clk}
get_property [all_clocks] set_uncertainty
get_property [all_clocks] hold_uncertainty

setAnlaysisMode -check_type setup
get_property [all_clocks] set_uncertainty

setAnlaysisMode -check_type hold
get_property [all_clocks] hold_uncertainty

clock transition and input transition

set_input_transition 0.5 [get_ports port_name]
set_clock_transition 0.5 clk

Duty cycle = Active pulse width / entire clock period
what is the duty cycle of a clock with the period of 10, and the waveform is {2 7}

Duty cycle = {falling edge -rising edge} / clock period

clock jitter:
from cycle to cycle clock period and duty cycle can change slightly due to clock generation circuitry
is called as jitter

skew: the difference in clock arrival time is called skew

Multiple clock domains:
worst-case data transfer:

1. find the LCM of both the clock periods
2. align the clock rising edge of both clocks

set_max_delay -from [all_registers -clock clk1 -clock_pins] -through U10/Y -to [all_registers -clock clk1 -clock_pins] 2 -combinational_from_to

report_timing --from [all_registers -clock clk1 -clock_pins] -through U10/Y -to [all_registers -clock clk1 -clock_pins] -path_type full_clock

Drive adjustment: The difference between the rise delay with load -rise delay with zero load

Script to report of the endpoints and startpoints slack of top 1000 failing paths

set rpt [report_timing -max_paths 1000 -max_slack 0 -collection]
foreach_in_collection r $rpt { puts "Endpoint: [get_property [get_property $r capturing_point] hierarchical_name] \t Startpoint: [get_property [get_property $r launching_point] hierarchical_name] \t Slack: [get_property $r slack]" }

Output:

Synopsis design constrains

Example SDC File:
create_clock  -name SYS_CLK -period 10 -waveform {0 0.5} [get_ports PORT_NAME]
create_generated_clock  -name GEN_SYS_CLK -source PORT_NAME  -divide_by 2 
create_clock -name V_SYS_CLK -period 10 -waveform {0 5}

set_input_delay -max 3 -clock SYS_CLK [get_ports port_name]

set_output_delay -max 7 -clock SYS_CLK [get_ports port_name]

set_max/min_delay -max 3 -clock SYS_CLK [get_pins Pin_name]
set_multicycle_path -setup 3 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_multicycle_path -hold 2 -from [get_clocks CLK1] -to [get_clocks CLK2]

set_driving_cell -lib_cell BUFX2  [get_ports Port_name]
set_load 0.9 [get_ports out[10]]

set_case_analysis 1 [get_ports SE]

set_case_analysis 0 [get_port TM]

set_dont_use [get_lib_cells RAM2P_128x16_ss_1v08_125c_syn/RAM2P_128x16]

set_propagated_clocks [get_clocks*]

set_disable_timing [get_cells cell_name]

set_clock_uncertainty 0.250 -setup [get_clocks CLK]
set_clock_uncertainty 0.100 -hold [get_clocks CLK]
set_max_delay 5.0 [get_ports port_name]
set_load 2 [get_ports port_name]
set_input_transition 1.0 -clock clk [get_ports port_name]

Synthesis

Synthesis

Tools used: Genus/RC compailer
What is Synthesis

• Synthesis is a process of converting RTL code to Gate_level_netlist is called synthesis

Why Synthesis:

• To manufacture the behavioral code ,so we are converting to Gate level netlist

Inputs to Synthesis 

• Libraries
• SDC
• RTL code (synthesizable)
• technology File
• Lef file

Outputs of Synthesis

• Synthesized SDC 
• Synthesized Netlist (.v)

Goals of Synthesis

• To get a gate level Netlist
• Inserting clock gates
• Logic optimization
• Inserting DFT logic
• Logic equivalence between RTL 
• The area will decide (area got reduced by doing the optimization)
• Gate count will decide (based on the logic and optimization process)

create a File with the name of flist we will include the all the Verilog netlists like top module sub-module netlists the below web address do point out the flist file

https://nagarajuphysicaldesign.blogspot.com/2019/11/flist.html

create one sdc file and you can define the clock in that file at clock port like
create_clock -name clk -period 10 -waveform {0 5}  [get_ports clock_port name}
the below path will address the sdc file

https://nagarajuphysicaldesign.blogspot.com/2019/11/synopsis-design-constrains.html

> genus -f scripts

after the synthesis it will provide the synthesized netlist, we will do the sanity checks in Genus for timing as well as design-related checks

1. Check_timing
2. Check_design 

• In flist file keep top-level netlist first and run the synthesis 
• genus provides the unresolved references for sub-modules which are defined in Top-level netlist
• 100% genus will provide the unresolved reference for all submodules which are defined in top module 
• If genus doesn't provide the unresolved references for specific submodule please check the netlist, if is there any ifdef statements are presented or not
• If the top-level netlist has ifdef statement is defined before for that particular submodule genus won't provide the unresolved references for that submodule you can define the ifdef statement name in scripts file by the following command
• read_hdl -f flist -define {"abcd" "efgh"}  
• If you get the unresolved references in the design you can include that module netlist in the flist file and re_run the synthesis until to clear the unresolved references.
• If your design has more flops you can create the block boxes 
• first, check for a two-dimensional array (2D_register) are there  in Verilog netlists, in netlist path, if the register count is more than two hundred  you can create it as a block box
• You can create an empty module for that and include in flist and rerun the synthesis, and it provides the empty module
• this empty module consists of the only module, instance name input-output and inout information it does not has any information 

Process of Synthesis

1. Translation
2. Mapping
3. Optimization

• If your design has constants you can remove by placing the buffers without any optimization

llength [get_db ports -if {.direction==in}]
llength[ [get_db ports -if {.direction==out}]
report_timing -lint .... will give the unconstrained path details

1. Translation:

• Process of converting behavioral code to generic Boolean algebra, It is a technology independent
• For Gtech library we don't have timing inforamtion

2. Mapping

• Selecting the suitable cell from the Technology library it is technology dependent based on input tool will pick the suitable cell from the lib

3. Optimization:

• Optimize the logic ,it will remove the  redundancy logic will be deleted
• Tool will optimize for the area power and performance.

4. Empty module:

• It has only inputs and outputs information, it doesn't have any logic inside the module definition.

5.Unresolved references

• Module definition is present but timing library is missing is called unresolved references 

6.Block_Box

• Macros are block boxes ,there is no functional information but it has timing info 

7.Elaborate:

• Translate the design into its GTECH representation
• Allows changing the parameters values defined in the source code replace the HDL arithmetical operators in the code with the design ware component
• It will check for the sub modules in the Top module ,if there are any gate-level netlists read in with the RTL files, Genus automatically links the cells to their references in the technology library during elaboration.
• It links the design automatically

8).link:  It will link the Design

9). what happens during optimization techniques

• Path adjustment
• Path grouping
• Re-timing
• Tns optimization
• Ungrouping

10). What are the different stages of Optimization in synthesis

• Architectural optimization
• Sharing the sub expressions
• Sharing the resources
• Selecting the design ware components
• After completion of this optimization  design is represented GTECH format
• Logical optimization 
• Will do Boolean algebraic optimization
• Gate level Optimization
• During this stage the logic is converted to logical gate level netlist
• Incremental optimization
• redundancy logic will converted to equivalent gate

11). What is retiming

• Retiming is an advanced optimization technique where registers are re-positioned to reduce cycle time or area without changing the input-output latency of the design. 
• This technique is best fitted for a design that can be pipe lined. 
• The drawback of this technique is, possible problem in formal verification.
• Retiming can be enabled at the top level or selective modules using the ‘retime’ attribute.
• Retiming can recover sequential area from a design with both easy to meet timing goals and a positive slack from the initial synthesis.
• Retiming a design that does not meet timing goals after the initial synthesis could impact total negative slack: the paths with the better slack can be “slowed down” to the range of worst negative slack

12).Path Adjust

• Tightening the constraint on a selective path will make the path become more critical and force Genus to work harder on it. 
• This trick can help closing timing for a small number of violating paths. 
• The following constraint needs to be set before mapping
• path_adjust -delay <> -from -to 

6).Boundary Optimization:

• Propagation of constant across the boundary
• Propagation of equal and opposite information across the hierarchy
• propagation of unconnected Port information across hierarchy
• Pushing of inverters across the hierarchy

13).Ungrouping :

• ungrouping merges the sub design of a given hierarchy into the parent cell or design ,it removers the hierarchical boundaries and allows design compiler to improve the timing by reducing the levels of logic and to improve the area and sharing logic

Few commands :

• check_timing_intent
• checkDesign -all

https://www.blogger.com/blog/post/edit/7948084828664881049/3698505313912971628#

Flist

/root/users/username/design/synthesis/rtl/verilog/submodulename.v
/root/users/username/design/synthesis/rtl/verilog/sub_modulename.v
/root/users/username/design/synthesis/rtl/verilog/design_name_Top.v

Representation of the Parasitic

Parasitic representation

DSPF: Detailed standard parasitics Format
RSPF: Reduced standard parasitics Format
SPEF: Standard parasitic extraction Format

• Standard parasitics Extraction Format interconnect parasitics depend on process. SPEF supports the specification of best-case, typical, and worst-case values. 
• These triplets are allowed for R, L and C values, port slews and loads. By providing a name map consisting of a map of net names and instance names to indices, the SPEF file size is made effectively smaller, and more importantly, all long names appear in only one place.

DSPF: Detailed standard parasitics Format:

• Detailed parasitics are represented in SPICE format, SPICE Comment statements are used to indicate the cell type, pin capacitance
• The resistance and capacitance values are in standard SPICE syntax and the cell instantiations are also included in this representation. 
• Merits:
• DSPF file can be used as an input to a SPICE simulator itself. 
• Drawback
• The DSPF syntax is too detailed and verbose with the result that the total file size for a typical block is very large.

RSPF: Reduced standard parasitics Format

• These parasitics are represented in reduced format and it involves in voltage-controlled current sources.
• Detailed parasitics are reduced and mapped into Reduced format it can be read into SPICE Simulators
• Drawbacks:
• Not represented for bidirectional signal flow

Assign statements

Netlist

If your Netlist has assign statements tool doesn't understand these statements, so you have to remove the assign statements by setting the below command/ replace the constants with buffers /add tie_cells

• set init_remove_assigns 1

The tool will replace the assigns with buffer

1. The default behavior of Verilog writer in innovus is to skip unconnected pins when writing out a Verilog netlist
2. setExportMode -fullPinout true
3. saveNetlist

How to remove assign statements that involve inout ports
The assign statement, in this case, can be removed using the insert_io_buffers utility
command:

• insert_io_buffers -isolate_top outs

• Removes assigns that involve only internal "wires".
  For example, in the code below, assign n2 = n1 is removed.
  module top();
    wire n1, n2;
    assign n2 = n1;
    BUFX2 u1(.Y(n1));
    BUFX2 u2(.A(n2));
    endmodule
  becomes
  module top();
    wire n1;
    BUFX2 u1(.Y(n1));
    BUFX2 u2(.A(n1));
    endmodule
• Removes assigns that involve only one port.
  For example, in the code below,  assign p1 = n1  is removed.
    module hier(p1);
    output p1;
    wire n1;
    assign p1 = n1;
     BUFX2 u1(.Y(n1));
    endmodule
  becomes
    module hier(p1);
    output p1;
     BUFX2 u1(.Y(p1));
    endmodule
  
  
• Rewires nets with feedthrough assigns that involve at least two ports, at some higher level:
  module hier2 (
            i,
            o);
       input i;
       output o;
       assign o = i ;
       BUFX2 u1 (.A(i));
    endmodule
    module hier (
            i,
            o);
       input i;
       output o;
  
  
       hier2 u1 (.i(i),
            .o(o));
    endmodule
    module top ();
       // Internal wires
       wire i;
       wire o;
       BUFX2 u1 (.Y(i));
       hier u2 (.i(i),
            .o(o));
       BUFX2 u3 (.A(o));
    endmodule
  
  
  becomes
  
  
  module hier2 (
            i,
            o);
       input i;
       output o;
  
  
       BUFX2 u1 (.A(i));
    endmodule
    module hier (
            i,
            o);
       input i;
       output o;
       hier2 u1 (.i(i));
    endmodule
    module top ();
       // Internal wires
       wire i;
  
  
       BUFX2 u1 (.Y(i));
       hier u2 (.i(i));
       BUFX2 u3 (.A(i));
    endmodule

Wire Load Models

NLDM: (Non-Linear Delay Model)

These NLDM models have been utilized when the effect of interconnect resistance is small. In the presence of resistive interconnect, the delay calculation methodologies retrofit the NLDM models by obtaining an equivalent effective capacitance at the output of the cell.

CCS Wire load Model
The given input transition time and output load, the output current waveform as a function of time is available.