Interview questions part 4

1). Steps involved in synthesis like compile, elaborate, link and then dc_compile for  optimization understand what happens in each stage 

Elaborate:

• It will check for the sub modules in the Top module ,if there are any gate-level netlists read in with the RTL files, Genus automatically links the cells to their references in the technology library during elaboration.
• Translate the design into its gtec representation
• allows changing the parameters values defined in the source code
• Replace the HDL arithmetical operators in the code with the design ware component
• It links the design automatically

link:  It will link the Design

2). what happens during optimization techniques

• Path adjustment
• Path grouping
• Re-timing
• Tns optimization
• Ungrouping

3). What are the different stages of Optimization in synthesis

• Boolean optimization (Architectural optimization)
• Incremental optimization

4). What is retiming

• Retiming is an advanced optimization technique where registers are repositioned to reduce cycle time or area without changing the input-output latency of the design. 
• This technique is best fitted for a design that can be pipe lined. 
• The drawback of this technique is, possible problem in formal verification.
• Retiming can be enabled at the top level or selective modules using the ‘retime’ attribute.
• Retiming can recover sequential area from a design with both easy to meet timing goals and a positive slack from the initial synthesis.
• Retiming a design that does not meet timing goals after the initial synthesis could impact total negative slack: the paths with the better slack can be “slowed down” to the range of worst negative slack

Path Adjust

• Tightening the constraint on a selective path will make the path become more critical and force Genus to work harder on it. 
• This trick can help closing timing for a small number of violating paths. 
• The following constraint needs to be set before mapping
• path_adjust -delay <> -from -to 

Boundary Optimization:

• Propagation of constant across the boundary
• Propagation of equal and opposite information across the hierarchy
• propagation of unconnected Port information across hierarchy
• Pushing of inverters across the hierarchy

Ungrouping :

• ungrouping merges the sub design of a given hierarchy into the parent cell or design ,it removers the hierarchical boundaries and allows design compiler to improve the timing by reducing the levels of logic and to improve the area and sharing logic