Check_design issues

 Check_design

• Unresolved References
• empty modules
• Constants
• Assign_statements
• undriven pins
• unloaded outputs
• unconstrained input pins
• Multi driven
• constant hierarchical pins

Multi_driven_nets :

• Why  multi driven nets will come
• If you have a block box module in the design ,Genus assumes all its ports as "inout" ports and this lead to the multi driven nets warning, to resolve this  you need to at least define the port definitions for the block box module

Assign_statements: 

• Assign statements causes feed through and we can replaced with Buffers

Report_timing :

report_timing command it will display the following information

• starting point
• End point
• path type
• path group
• nets
• cells
• capacitance
• transition
• data arrival time
• data required time
• library setup time
• insertion delay
• output delay
• input delay
• slack

report_qor:

report_qor will give the following information 

• cell count
• sequential cell count
• combinational cells count
• WNs
• TNs
• No of paths are failing