Low Power Cells

 Low power cells

• Clock gating cells
• Power Gating
• Level shifters
• Retention registers
• Switch cells

Clock gating cells

• Clock gating can be inserted without changing the function of the logic
• Add clock gating in clock path to prevent the clock cycles
• clock gating cells are used to reduce the dynamic power

Power gating cells

• Which is used to shutoff the Power supply to the particular region 
• Power gates are use to reduce the leakage Power
• Header switch and Footer Switch
• Header switch will connect between VDD and PMOS 
• Footer Switch will connect between NMOS and VSS
• When SLEEP = 0 transistor will work normally (SLEEP 0 and 1 is based on power control management)
• When SLEEP =1  transistor will turn off
• SLEEP transistors are used to control Power to the selected blocks

• Disadvantages: To turn on the PMOS it may take long time it causes more IR drop compare to NMOS
• More number of transistor at time to turn ,it means more current is required to turn at that time drop may come

Level Shifters

• Level shifter's are classified into two types
• High_to_low Level shifter
• Low_to_High Level shifter
• High to low Level shifter is used The signal going from the high voltage domain to low voltage domain the gate of the transistor may damage in the receiving domain ,or cause signal EM that's why we use the High to low Level shifter
• Low to high level shifter is used when ,the potential difference between the two voltage domain is greater than the subtraction of ground bounce % in VDDh from threshold voltage , low voltage signal is driving the high voltage domain ,may cause crow bar currents to avoid we use this Level Shifter
• VDDH-VDDL > Vth-{%of ground bounce of VDDH}
• One of the fundamental reason is that example 1Vsignal is driving the  1.5V gate will turn on both NMOS and CMOS it may cause crowbar current
• To meet certain requirements ,signal rise or fall time degradation between the driving cell in one domain and the receiving into another domain it may cause Timing Violations
• When the signal is going from 1V voltage domain to 1.5V voltage domain are vise verse we use Level Shiters
• Normally we can put the level shifter in three places like in transmitter domain or in receiver domain or between the Domains
• Basically Level shifters are placed in the destination Domain

Retention Registers (Shadow Register)

• while doing any job in the device , when power supply of the device is turn off the state of the info is lost, to resume the state of the info when its Power up 
• The block must have its state restore from external source build up its state from the reset condition
• we can keep inside the always on logic
• It will placed in placement stage
• Height of the retention flop is double of the standard cell row (For 45nm 1.71 is the row height ) 
• Flop height is equals to 2*row height 

Switch cells:

• Switch cells are used to Power up / down for the rails to the particular block we use switch cells
• which are placed under the stripes
• Switch cell has two Power inputs and one output
• External power input, PSO for signal, PSO_out , VDD, VSS
• Inputs are control input and power supply 
• Output is power output (input voltage is equal to output voltage)
• Which are placed in ring fashion or column fashion or daisy chain format
• Which are placed in daisy chain format to switch on the rails
• More number of switch cells are required to turn on the rails ,at a time more logic need to turn on , so if we provide less it cause IR drop issue
• Got placed in Power plan stage
• retention flops ,Always_on_cells, level shifters and isolation cells are placed at placement stage