Script for design to list the cellls and its count

dbGet commands  

#!/usr/bin/tclsh

set instances_name [dbGet top.insts.name]

set instances_count [llength $instances_name]

set sequential_cells [dbGet [dbGet -p2 top.insts.cell.IsSequential 1].name]

set sequential_count [llength $sequential_cells]

set buffers [dbGet [dbGet -p2 top.insts.cell.isBuffer 1].name]

set buffers_count [llength $buffers]

set Power_switch_cells [dbGet [dbGet -p2 top.insts.cell.isPowerSwitch  1].name]

set Power_switch_count [llength $Power_switch_cells]

set inverter_cells [dbGet [dbGet -p2 top.insts.cell.isInverter  1].name]

set inverter_count [llength $inverter_cells]

set level_shifter_cells [dbGet [dbGet -p2 top.insts.cell.isLevelShifter 1].name]

set level_shifter_count [llength $level_shifter_cells]

set retention_cells [dbGet [dbGet -p2 top.insts.cell.isRetention  1].name]

set retention_count [llength $retention_cells]

set isolation_cells [dbGet [dbGet -p2 top.insts.cell.isIsolationCell  1].name]

set isolation_count [llength $isolation_cells]

set physical_cells [dbGet [dbGet -p top.insts.isPhysOnly 1].name]

set physical_cells_count [llength $physical_cells]

puts "total instances list is :$instances_name"

puts "Total sequential cells list is: $sequential_cells"

puts $isolation_cells

puts $Power_switch_cells

puts $buffers

puts $inverter_cells

puts $level_shifter_cells

puts $retention_cells

puts $physical_cells

puts "total instances count in the design is : $instances_count"

puts "Total sequential cells count is :$sequential_count"

puts "Total Buffer cells count is:$buffers_count"

puts "Total power switch cells count is:$Power_switch_count"

puts "Total inverter cells count is:$inverter_count"

puts "Total level shifter cells count is:$level_shifter_count"

puts "Total retention cells count is:$retention_count"

puts "Total isolation cells count is:$isolation_count"

puts "Total Physical_Cells is : $physical_cells_count"

set combo_cells_count [expr $instances_count - $sequential_count - $buffers_count - $Power_switch_count - $inverter_count - $level_shifter_count - $retention_count - $isolation_count - $physical_cells_count]

puts "combinational cells count is : $combo_cells_count"

Fabrication Steps

Etching

In the etching step, a liquid (“wet etching”) or plasma (“dry etching”) chemical agent removes the uppermost layer of the substrate in the areas that are not protected by photo­ resis

Diffusion

The basic principle underlying this process is that the dopant atoms migrate from a region of high concenfration to the region of low concentration In simple, diffiision is the process of introducing controlled amounts of dopants into the semiconductors.

Interview questions part 4

1). Steps involved in synthesis like compile, elaborate, link and then dc_compile for  optimization understand what happens in each stage 

Elaborate:

• It will check for the sub modules in the Top module ,if there are any gate-level netlists read in with the RTL files, Genus automatically links the cells to their references in the technology library during elaboration.
• Translate the design into its gtec representation
• allows changing the parameters values defined in the source code
• Replace the HDL arithmetical operators in the code with the design ware component
• It links the design automatically

link:  It will link the Design

2). what happens during optimization techniques

• Path adjustment
• Path grouping
• Re-timing
• Tns optimization
• Ungrouping

3). What are the different stages of Optimization in synthesis

• Boolean optimization (Architectural optimization)
• Incremental optimization

4). What is retiming

• Retiming is an advanced optimization technique where registers are repositioned to reduce cycle time or area without changing the input-output latency of the design. 
• This technique is best fitted for a design that can be pipe lined. 
• The drawback of this technique is, possible problem in formal verification.
• Retiming can be enabled at the top level or selective modules using the ‘retime’ attribute.
• Retiming can recover sequential area from a design with both easy to meet timing goals and a positive slack from the initial synthesis.
• Retiming a design that does not meet timing goals after the initial synthesis could impact total negative slack: the paths with the better slack can be “slowed down” to the range of worst negative slack

Path Adjust

• Tightening the constraint on a selective path will make the path become more critical and force Genus to work harder on it. 
• This trick can help closing timing for a small number of violating paths. 
• The following constraint needs to be set before mapping
• path_adjust -delay <> -from -to 

Boundary Optimization:

• Propagation of constant across the boundary
• Propagation of equal and opposite information across the hierarchy
• propagation of unconnected Port information across hierarchy
• Pushing of inverters across the hierarchy

Ungrouping :

• ungrouping merges the sub design of a given hierarchy into the parent cell or design ,it removers the hierarchical boundaries and allows design compiler to improve the timing by reducing the levels of logic and to improve the area and sharing logic

Timing violations Fixing Orders

 Order of Fixing the timing violations

• Cross talk Noise 
• Bottleneck analysis
• Fan-out
• capacitance
• transition
• hold time violation
• setup time violations

SETUP time Violations Fixing and How it impact on the design

                         SETUP TIME Violations fixing Techniques

The following techniques are used to fix the Setup time violations

1. Up-size the cell
2. HVT to LVT conversion
3. Add buffer on Data path

1).Up-size the buffer

• get_cells
• get_lib_cells -of_object cell_name  (which cell you want to up-size NOR2X0_HVT)
• get_alternative_lib_cells cell_name
• size_cell cell_name saed32hvt_ff1p16vn40c/NOR4X0_HVT (corresponding cell library with cell name )

Disadvantages:

• Cell size may increase 
• Location of the cell pins will change
• Nearer cells will move
• Transition time will increase it means data comes early it will impact on the hold

2). VT Swapping (HVT to LVT conversion)

• get_cells
• get_lib_cells -of_objects U453 (cell name NOR4X0_LVT)
• size_cell U453 NOR4X0_LVT  (U453 Instance name)

3).Add buffer

• insert_buffer net_name BUFX4

Disadvantages : 

• If the cell delay is more than the net delay will get the more timing violation
• If the net length is more, then only we will add the buffer other wise timing violations goes more worst 

Note: Here cell name means Instance name

4). Creating the Bound

• createInstGroup group_name
• createInstGroup group_name -guide { co- ordinates}
• addInstGroup group_name {instances names}

5). Up_size the flop

• If there is no possibility with the logic to up_size you can up_size the Launch Flop
• It will benefit just 3 to 10 ps
• May effect to Hold time violation

Report_annatoted_delay

 Report_annotated_delay 

• Annotated delay means To set cell/net delay.
• To set a cell delay, specify the delay from a cell input to an output of the same cell. 
• To set a net delay, you specify the delay from a cell output to a cell input.
• In a design that uses SDF-annotated delays on all arcs or almost all arcs, such as 95% or more
• Annotated delay Means  :RC values are applied properly 
• Non -Annotated Delay means: RC values are not applied properly 
• For any arcs that are not annotated, Sign-off Tool  estimates the delay and output slew using the best available input slew. 
• For a block of arcs that are not annotated, Tool propagates the worst slew throughout the block.

Voltus

 VOLTUS

Inputs for VOLTUS (power analysis):

• Technology lefs

• Tech lef

• Macro lef

• Decap lef

• Buf lef

•  Libraries

• Verilog netlist

• DEF (data exchange format)

• SPEF (standard parasitic extraction format)

• CPF (common power factor)

Commands used in voltus

• read_lib -lef $lefs

• read_view_definition ../design/viewDefinition.tcl

• read_verilog ../design/postRouteOpt.enc.dat/Top.v.gz

• read_def ../design/routed_data.def.gz

• read_power_domain -cpf ../design/Top.cpf

• Read_spef ../design/postRouteOpt_RC_wc_125.spef.gz

How to go back from routing db to powerPlan

 To go to power plan 

editDelete -type Regular

deleteShield -nets *

selectInst *

deselectInst u0

deselectInst ring/PSO_RING_psoI_PD_ring_1_RING_SWITCH*

deselectInst ring/PSO_RING_psoI_PD_ring_1_RING_CORNER*

deselectInst column/PSO_COLUMN_psoI_PD_column_1_HEADER_SWITCH*

dbSet selected.InstTerms.Inst.pstatus placed

dbSet selected.InstTerms.Inst.pstatus unplaced

deleteFillers

Few shortcuts for manual editing

 Short cuts

1. a  to select

2. s to stretch the wire

3. Shift +a edit wire , press e to entering  into the edit route

4. K for scale

5. Shift+k to remove the scale markers in the design window 

Commands to add functional mode

Commands to add Functional ECO

• detach_net read_spi SPI_INST/A/B1

• add_inst ecoAND FreePDK45_lib_v1.0/AND2_X1

• add_net New_net

• attach_net New_net ecoAND/A1

• attach_net New_net SPI_INST/A/B1

• attach_net read_spi ecoAND/ZN

• attach_net ibias ecoAND/A2

By using above commands we can add a cell in between modules. This we called it as Functional ECO

View Defination file

• Defining the PVT corners
• Delay corners
• Constraining the modes
• Creating the views
• Setting the analysis views

1. Mode: Whether it is a functional mode/ test mode /scan mode
2. corners : Based on Pvt will define the corners
3. Views  : The combination of mode and corners is called View

Check_design issues

 Check_design

• Unresolved References
• empty modules
• Constants
• Assign_statements
• undriven pins
• unloaded outputs
• unconstrained input pins
• Multi driven
• constant hierarchical pins

Multi_driven_nets :

• Why  multi driven nets will come
• If you have a block box module in the design ,Genus assumes all its ports as "inout" ports and this lead to the multi driven nets warning, to resolve this  you need to at least define the port definitions for the block box module

Assign_statements: 

• Assign statements causes feed through and we can replaced with Buffers

Report_timing :

report_timing command it will display the following information

• starting point
• End point
• path type
• path group
• nets
• cells
• capacitance
• transition
• data arrival time
• data required time
• library setup time
• insertion delay
• output delay
• input delay
• slack

report_qor:

report_qor will give the following information 

• cell count
• sequential cell count
• combinational cells count
• WNs
• TNs
• No of paths are failing

ICC_Commands

Delay calculations

• get_cells *
• get_pins -of_objects instance_name
• report_delay_calculation -from ABC/a -to ABC/y

swapping from LVT/HVT to HVT/LVT

• get_cells *
• get_lib_cells -of_objects instance_name
• size_cell instance_name lib_name lib_name
• get_lib_cells -of_objects instance_name

how to calculate the gate count

• gate_count = (total area/Nand gate area)

How to find the lib_cells of a cell

• get_lib_cells */*DEL*
• all_macro_cells
• size_of_collection [all_macro_cells]

How to add buffer

Adding Buffer (ICC)

• get_nets -of_objects [get_pins -of_object pin_name -filter "direction==out"]
• get_buffers
• insert_buffers net_name BUFX4
• update_timing
• report_timing

Low Power Cells

 Low power cells

• Clock gating cells
• Power Gating
• Level shifters
• Retention registers
• Switch cells

Clock gating cells

• Clock gating can be inserted without changing the function of the logic
• Add clock gating in clock path to prevent the clock cycles
• clock gating cells are used to reduce the dynamic power

Power gating cells

• Which is used to shutoff the Power supply to the particular region 
• Power gates are use to reduce the leakage Power
• Header switch and Footer Switch
• Header switch will connect between VDD and PMOS 
• Footer Switch will connect between NMOS and VSS
• When SLEEP = 0 transistor will work normally (SLEEP 0 and 1 is based on power control management)
• When SLEEP =1  transistor will turn off
• SLEEP transistors are used to control Power to the selected blocks

• Disadvantages: To turn on the PMOS it may take long time it causes more IR drop compare to NMOS
• More number of transistor at time to turn ,it means more current is required to turn at that time drop may come

Level Shifters

• Level shifter's are classified into two types
• High_to_low Level shifter
• Low_to_High Level shifter
• High to low Level shifter is used The signal going from the high voltage domain to low voltage domain the gate of the transistor may damage in the receiving domain ,or cause signal EM that's why we use the High to low Level shifter
• Low to high level shifter is used when ,the potential difference between the two voltage domain is greater than the subtraction of ground bounce % in VDDh from threshold voltage , low voltage signal is driving the high voltage domain ,may cause crow bar currents to avoid we use this Level Shifter
• VDDH-VDDL > Vth-{%of ground bounce of VDDH}
• One of the fundamental reason is that example 1Vsignal is driving the  1.5V gate will turn on both NMOS and CMOS it may cause crowbar current
• To meet certain requirements ,signal rise or fall time degradation between the driving cell in one domain and the receiving into another domain it may cause Timing Violations
• When the signal is going from 1V voltage domain to 1.5V voltage domain are vise verse we use Level Shiters
• Normally we can put the level shifter in three places like in transmitter domain or in receiver domain or between the Domains
• Basically Level shifters are placed in the destination Domain

Retention Registers (Shadow Register)

• while doing any job in the device , when power supply of the device is turn off the state of the info is lost, to resume the state of the info when its Power up 
• The block must have its state restore from external source build up its state from the reset condition
• we can keep inside the always on logic
• It will placed in placement stage
• Height of the retention flop is double of the standard cell row (For 45nm 1.71 is the row height ) 
• Flop height is equals to 2*row height 

Switch cells:

• Switch cells are used to Power up / down for the rails to the particular block we use switch cells
• which are placed under the stripes
• Switch cell has two Power inputs and one output
• External power input, PSO for signal, PSO_out , VDD, VSS
• Inputs are control input and power supply 
• Output is power output (input voltage is equal to output voltage)
• Which are placed in ring fashion or column fashion or daisy chain format
• Which are placed in daisy chain format to switch on the rails
• More number of switch cells are required to turn on the rails ,at a time more logic need to turn on , so if we provide less it cause IR drop issue
• Got placed in Power plan stage
• retention flops ,Always_on_cells, level shifters and isolation cells are placed at placement stage