Sanity Checks:
sanity checks qualify the netlist in terms of timing ,checks the issues related to library files and constraints file etc.
Techniques to resolve the sanity checks and its clear explanation
sanity checks qualify the netlist in terms of timing ,checks the issues related to library files and constraints file etc.
Techniques to resolve the sanity checks and its clear explanation
- Check_timing -verbose
- CheckDesign -all
- Check_library
- Check_legality
- Check_Netlist
- Report_qor
- Report_timing
1.Check_timing:
Check_timing will checks the below following Issues
- Clock wave form not reaching to the flops
- Combinational loops
- Clock is expected but clock is not reaching to the flops/unconstrained paths
- No drive assertion
- No external input delay on the specified ports
- No external output delay on the specified Ports
- Unconstrained signal arriving at end points/ports
- Ideal clocks
- Multi_driven_nets
Issues clear Explanation and resolve techniques
Clock wave form not reaching to the flops:
Clock wave form not reaching to the flops:
- It means clock is not yet created ,so we will create a new clock to resolve this issues
- create_clock -name CLK -period 10 -waveform {0 5} -source [get_ports clock_port]
Combinational loops:
- A combinational loop is formed when a signal can reach back to itself without encountering any sequential device along the path.
- This loop should be broken for timing analysis, you can manually choose which segment to disable and explicitly let the timing analysis tool know.so that any meaning full path is not excluded from the timing analysis.
- By default innovus/tempus tool will identify the combinational loop in the design and breaks the loop at different arbitrary point.
- set_disable_timing -from A -to Y [get_cells cell_name]
Clock is expected but clock is not reaching to the flops/unconstrained paths:
set b [get_object_name $a]
puts "$b"
}
- unconstrained paths means clock reaching but waveform is not reaching to the that flop D pin
Why proper clock wave form is not reaching to the reference pin/port
reasons are follows
- If there is a case analysis
- Disablement the timing arc
- set_clock_sense
- we can check for that pin whether the clock is reaching to the flop or not by following command
- get_property [get_pins Reg/D] clock_sources
- get_property [get_pins abcd/ck] clocks
- find all fan in to that flop
set b [get_object_name $a]
puts "$b"
}
- select any one of the q pin and generate the clock to resolve this issue
- find the clock sources to the selected flop and where the clock sources is same then for that master clock you can create the generated clock to resolve the issue
- create_generated_clock -name G_CLK -divided_by 2 -source CLK [get_pins reg/Q]
No external input delay on the specified ports:
By setting the input delay to that port, to resolve the issue
- set_input_delay -max 3 -clock CLK [get_ports port_name] {30% of the clock period}
- set_input_delay -min 2 -clock CLK [get_ports port_name] {
30% of the clock period}
No external output delay on the specified Ports
Unconstrained signal arriving at end points/ports
Unconstrained signal arriving at end points/ports
If no external output delay issue is on pin you can create the generated clock or it is on the port you can give the output delay constraints
- set_output_delay -max 7 -clock CLK [get_ports port_name] {70% of the clock period}
- set_output_delay -min5 -clock CLK [get_ports port_name] {
70% of the clock period}
No drive assertion
- It means no drive is specified for ports we will get this issues
- set_driving_cell -lib_cell BUFX2 [get_ports port_name]
- instead of specifying the driving cell command at input pin/port you can give the set_input_transition command to resolve this violations
Ideal Clock
set_propagated [get_clocks all_clocks]
set_propagated [get_clocks all_clocks]
