To report worst slack for a particular timing groups

Write a script to report the clock group worst slack

set_global timing_report_group_based_mode true
                foreach_in_collection path [sort_collection [report_timing -max_slack 100-collection]            path_group] {
                               set size [sizeof_collection $path]
                               set path_group [get_property -quiet $path path_group_name]
                               set wns [get_property -quiet $path slack]
                               set view [get_property -quiet $path view_name]
                               puts "Clock group: $path_group View: $view WNS: $wns"
}

Script to report cell delays

Write a TCL script to report the  Cell delay

set paths_rpt   [report_timing -collection -max_paths 10000 -max_slack 5 -path_group r2r]

foreach_in_collection timing_path $paths_rpt {
                  foreach_in_collection tp [get_property $timing_path timing_points] {
                        set delay [get_property $tp delay]
                        if {$delay > 0.1} {
                        Puts "[get_property $tp hierarchical_name] [get_property $tp delay]"
            }
       }
  }

Script to print the Begning Point,Ending point and Slack

 To report the beging Point endpoint and slack for the particular timing path groups

set   timing_paths  [report_timing -max_paths 1000 -max_slack 0 -collection -path_group r2r]                

        foreach_in_collection r $rpt { 

             puts "Endpoint: [get_property [get_property $r capturing_point] hierarchical_name] \t 

                     Startpoint: [get_property [get_property $r launching_point] hierarchical_name] \t 

                      Slack:   [get_property $r slack]" }

TAR

tar -cvf filename.tar filename
tar -xvf filename.tar

Static Timing Analysis Overview

Static timing Analysis and issues solving techniques and commands

Inputs For Static timing Analysis

• Verilog netlist (.V)
• Library files (.LIB)
• SPEF (standard parasitic extraction files) (.SPEF)
• DEF (design exchange format) (.DEF)
• SDC (synopsys Design Constraints) (.SDC)

Sanity Checks

• Check_timing
• checkDesign -all
• checkLibrary
• All_analysis_view
• report_annotated_delay

1.Check_timing : issues

• Unconstrained endpoint
• Clock_expecting
• No drive assertion
• Ideal wave forms
• Input delay 
• Timing Loops

Unconstrained endpoint & clock_expecting

Fixing techniques :

• For port we will create the clocks
• For pin we will createthe generated clocks

Example to create generated clock : check_timing -verbose > check_timing.rpt1

get_property [get_pins reg/CK ] clock_sources

foreach_in_collection a [all_fanin -to reg/CK] {

puts [get_object_name $a]

}

get_property [get_pins reg[0]/Q ] clock_sources

create_generated_clock -source clk -divide_by 2 -name nag_gen_clk1 [get_pins reg[0]/Q ]

No drive assertion: 

Set_drive 100 [get_pins pin_name]

Set_input_delay -clock V_clk  -add_delay 1.2 [get_pins /ports pin/port_name]

Ideal waveforms:

Set_propageted_clocks [get_clocks*]

Timing Loops

Timing_enable_mmmc_loop_handling true

Set_disable_timing [get_cells cell_name]

2)checkDesign -all

 It will give all design statistics 

• Macro cell count 
• Combinational 
• Sequential cell count
• Instance count 
• Area
• Floating pins  
• Unresolved References

3). All_analysis_views

It will display all the analysis views 

• Av_max1 , av_max2, av_max3 ,av_min1,av_min2
  
  

If we have more analysis views you can set the view and debug the timing issues

How to set the analysis views

Set_analysis_view -setup [list av_max1] -hold [list av_min1]

Timing Fixing techniques

Commands to report the timing violations

Report_timing 

Report_timing -early

Report_timing -early -max_paths 100 -nworst 10 -collection

Report_timing -early -path_group r2r -max_paths 100 -nworst 20 -path_type full_clock

Report_timing -late -path_group r2r -max_paths 100 -nworst 20 -path_type full_clock

report_constraint -all_violators -drv_violation_type max_transition

report_constraint -all_violators -drv_violation_type max_cpacitance

report_constraint -all_violators -drv_violation_type max_fanout

report_constraint -all_violators -early

report_constraint -all_violators -late

Report_timing -late -collection

Report_analysis_summary -late

Report_analysis_summary -early

ECO DRV's, HOLD & SETUP FIXING

#### system generated file##################

write_eco_opt_db

set_eco_opt_mode -load_eco_opt_db ecoTimingDB/

eco_opt_design -hold

#### individual own name ##############################

set_eco_opt_mode -save_eco_opt_db file_name

write_eco_opt_db

eco_opt_design -hold/setup/drv

The above commands will generate the three files ,They are 

Innovus.tcl

Tempus.tcl

ecoTimingDB

###########By manual fixing of setup /hold/drv################

Add_repeater -term pin/name -cell BUX_16 //adding buffer

Change_cell -inst instance_name  -cell BUX_16 // cell swapping

Change_cell -inst instance_name -down/upsize_cell //up_sizing//down_sizing

Dumping the Eco's

Write_eco  -format innovus -out Eco_DRV_innovus.tcl

write_eco -format tempus -out Eco_DRV_tempus.tcl

Useful COMMANDS

• filter_collection [all_registers] "is_memory_cell==true"
• report_timing -collection
• get_arcs
• get_cells
• all_instances
• all_registers
• all_fanin/all_fanout -only_cells
• get_clocks / get_generated_clocks /all_clocks
• get_designs
• lib_timing_arc 
• get_lib_arcs
• get_lib_cells
• get_libs
• get_nets
• all_connected
• To get the Path groups, get_path_groups
• pg_net Power / Ground nets get_pg_nets
• pg_pin Power / Ground pins get_pg_pins
• lib_pg_pin Power/Ground pins in Library get_lib_pg_pins
• get_pins
• all_fanin
• all_fanout
• get_property [get_clocks clk] period 
• get_ports / all_inputs / all_outputs / all_connected /
• group_path -name r2r -from [all_registers] -to [all_registers]
• group_path -name r2o -from [all_registers] -to [all_outputs]
• group_path -name i20 -from [all_inputs] -to [all_outputs]
• group_path -name i2r -from [all_inputs] -to [all_registers]
• filter_collection [all_registers] "is_memory_cell==true" 
• report_property [get_cells clock_cell_1] -property_list {ref_lib_cell_name area}
• get_property [get_clocks gen_clock1] clock_sources 
• get_property [get_clocks gen_clock1] sources 
• get_property [get_property [get_clocks gen_clock1] sources] object_type 
• set worst_path [report_timing –collection]
• get_object_name [get_property $worst_path capturing_clock]
• get_property [get_property $worst_path capturing_clock] object_type
• sort_collection [get_ports *] {direction full_name}
• Report_delay_calculation -from abc/a -to adc/b
• report_timing -path_type end_slack_only -early 
• report_timing -path_type end_slack_only -early -max_paths
• report_timing -path_group r2r -path_type full_clock -format {instances arc cell delay arrival required slew fanout net incr_delay}
• get_pins -hier -filter "hierarchical_name =~ */D" to report all_end_points 

How to balance the insertion delay of two different clocks with CCOpt

create_ccopt_skew_group -name clk2 -sources clk2 -auto_sinkscreate_ccopt_skew_group -name clk1 -sources clk1 -auto_sinkscreate_ccopt_skew_group -name ClockGroup000 -balance_skew_groups {clk1 clk2}

• we put the max_delay constraint
• false path
• synchronizers
• min delay

SETUP FIXING TECHNIQUES

Setup timing violations fixing techniques:

• Upsize the cell
• Swapping the cell foot print from HVT to LVT
• Add Buffer Based on the net length if the net length is more than the buffer delay we can add the buffer otherwise it will increase the violation timing
• Specify Net weight : Means We are giving the priority of the net to route the top metal metal layers.
• Specify net guide
• Creating the bound
• Upsize the launch flop
• Usefull Skew
• Based on top level decreasing the frequency
• Pipe Lining process

Note:
Bound ,Net weight and Net guide should give before Placement stage
Remaining techniques will applicable after the routing {ECO stage}